From: Dong Aisheng <aisheng.dong@nxp.com> To: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-mmc@vger.kernel.org, Dong Aisheng <aisheng.dong@nxp.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <kernel@pengutronix.de>, Fabio Estevam <fabio.estevam@nxp.com> Subject: [PATCH RESEND v4 08/18] arm64: dts: imx8: add conn lpcg clocks Date: Thu, 26 Nov 2020 18:58:50 +0800 [thread overview] Message-ID: <20201126105900.26658-9-aisheng.dong@nxp.com> (raw) In-Reply-To: <20201126105900.26658-1-aisheng.dong@nxp.com> Add conn lpcg clocks Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- ChangeLog: v2->v3: * update to use clock-indices property instead of bit-offset property v1->v2: * Use old SCU clock binding temporarily to avoid build warning due to SCU clock cell will be changed to 2. * add power domain propertyv1->v2: --- .../boot/dts/freescale/imx8-ss-conn.dtsi | 104 +++++++++++++++++- 1 file changed, 101 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 8691a43882fd..4220a5cdc249 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -4,15 +4,34 @@ * Dong Aisheng <aisheng.dong@nxp.com> */ +#include <dt-bindings/clock/imx8-lpcg.h> +#include <dt-bindings/firmware/imx/rsrc.h> + conn_subsys: bus@5b000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; - conn_lpcg: clock-controller@5b200000 { - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; + conn_axi_clk: clock-conn-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <333333333>; + clock-output-names = "conn_axi_clk"; + }; + + conn_ahb_clk: clock-conn-ahb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <166666666>; + clock-output-names = "conn_ahb_clk"; + }; + + conn_ipg_clk: clock-conn-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <83333333>; + clock-output-names = "conn_ipg_clk"; }; usdhc1: mmc@5b010000 { @@ -83,4 +102,83 @@ conn_subsys: bus@5b000000 { power-domains = <&pd IMX_SC_R_ENET_1>; status = "disabled"; }; + + /* LPCG clocks */ + conn_lpcg: clock-controller-legacy@5b200000 { + reg = <0x5b200000 0xb0000>; + #clock-cells = <1>; + }; + + sdhc0_lpcg: clock-controller@5b200000 { + reg = <0x5b200000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_SDHC0_CLK>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, + <IMX_LPCG_CLK_5>; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; + }; + + sdhc1_lpcg: clock-controller@5b210000 { + reg = <0x5b210000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_SDHC1_CLK>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, + <IMX_LPCG_CLK_5>; + clock-output-names = "sdhc1_lpcg_per_clk", + "sdhc1_lpcg_ipg_clk", + "sdhc1_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_1>; + }; + + sdhc2_lpcg: clock-controller@5b220000 { + reg = <0x5b220000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_SDHC2_CLK>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, + <IMX_LPCG_CLK_5>; + clock-output-names = "sdhc2_lpcg_per_clk", + "sdhc2_lpcg_ipg_clk", + "sdhc2_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_2>; + }; + + enet0_lpcg: clock-controller@5b230000 { + reg = <0x5b230000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>, + <&clk IMX_CONN_ENET0_ROOT_CLK>, + <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, + <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>, + <IMX_LPCG_CLK_5>; + clock-output-names = "enet0_ipg_root_clk", + "enet0_tx_clk", + "enet0_ahb_clk", + "enet0_ipg_clk", + "enet0_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_ENET_0>; + }; + + enet1_lpcg: clock-controller@5b240000 { + reg = <0x5b240000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>, + <&clk IMX_CONN_ENET1_ROOT_CLK>, + <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, + <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>, + <IMX_LPCG_CLK_5>; + clock-output-names = "enet1_ipg_root_clk", + "enet1_tx_clk", + "enet1_ahb_clk", + "enet1_ipg_clk", + "enet1_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_ENET_1>; + }; }; -- 2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: Dong Aisheng <aisheng.dong@nxp.com> To: devicetree@vger.kernel.org Cc: Dong Aisheng <aisheng.dong@nxp.com>, Mark Rutland <mark.rutland@arm.com>, linux-mmc@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, linux-imx@nxp.com, Sascha Hauer <kernel@pengutronix.de>, Fabio Estevam <fabio.estevam@nxp.com>, Shawn Guo <shawnguo@kernel.org>, linux-arm-kernel@lists.infradead.org Subject: [PATCH RESEND v4 08/18] arm64: dts: imx8: add conn lpcg clocks Date: Thu, 26 Nov 2020 18:58:50 +0800 [thread overview] Message-ID: <20201126105900.26658-9-aisheng.dong@nxp.com> (raw) In-Reply-To: <20201126105900.26658-1-aisheng.dong@nxp.com> Add conn lpcg clocks Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- ChangeLog: v2->v3: * update to use clock-indices property instead of bit-offset property v1->v2: * Use old SCU clock binding temporarily to avoid build warning due to SCU clock cell will be changed to 2. * add power domain propertyv1->v2: --- .../boot/dts/freescale/imx8-ss-conn.dtsi | 104 +++++++++++++++++- 1 file changed, 101 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 8691a43882fd..4220a5cdc249 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -4,15 +4,34 @@ * Dong Aisheng <aisheng.dong@nxp.com> */ +#include <dt-bindings/clock/imx8-lpcg.h> +#include <dt-bindings/firmware/imx/rsrc.h> + conn_subsys: bus@5b000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; - conn_lpcg: clock-controller@5b200000 { - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; + conn_axi_clk: clock-conn-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <333333333>; + clock-output-names = "conn_axi_clk"; + }; + + conn_ahb_clk: clock-conn-ahb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <166666666>; + clock-output-names = "conn_ahb_clk"; + }; + + conn_ipg_clk: clock-conn-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <83333333>; + clock-output-names = "conn_ipg_clk"; }; usdhc1: mmc@5b010000 { @@ -83,4 +102,83 @@ conn_subsys: bus@5b000000 { power-domains = <&pd IMX_SC_R_ENET_1>; status = "disabled"; }; + + /* LPCG clocks */ + conn_lpcg: clock-controller-legacy@5b200000 { + reg = <0x5b200000 0xb0000>; + #clock-cells = <1>; + }; + + sdhc0_lpcg: clock-controller@5b200000 { + reg = <0x5b200000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_SDHC0_CLK>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, + <IMX_LPCG_CLK_5>; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; + }; + + sdhc1_lpcg: clock-controller@5b210000 { + reg = <0x5b210000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_SDHC1_CLK>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, + <IMX_LPCG_CLK_5>; + clock-output-names = "sdhc1_lpcg_per_clk", + "sdhc1_lpcg_ipg_clk", + "sdhc1_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_1>; + }; + + sdhc2_lpcg: clock-controller@5b220000 { + reg = <0x5b220000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_SDHC2_CLK>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, + <IMX_LPCG_CLK_5>; + clock-output-names = "sdhc2_lpcg_per_clk", + "sdhc2_lpcg_ipg_clk", + "sdhc2_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_2>; + }; + + enet0_lpcg: clock-controller@5b230000 { + reg = <0x5b230000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>, + <&clk IMX_CONN_ENET0_ROOT_CLK>, + <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, + <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>, + <IMX_LPCG_CLK_5>; + clock-output-names = "enet0_ipg_root_clk", + "enet0_tx_clk", + "enet0_ahb_clk", + "enet0_ipg_clk", + "enet0_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_ENET_0>; + }; + + enet1_lpcg: clock-controller@5b240000 { + reg = <0x5b240000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>, + <&clk IMX_CONN_ENET1_ROOT_CLK>, + <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, + <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>, + <IMX_LPCG_CLK_5>; + clock-output-names = "enet1_ipg_root_clk", + "enet1_tx_clk", + "enet1_ahb_clk", + "enet1_ipg_clk", + "enet1_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_ENET_1>; + }; }; -- 2.23.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-11-26 11:17 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-26 10:58 [PATCH RESEND v4 00/18] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:58 ` [PATCH RESEND v4 01/18] dt-bindings: mmc: imx: fix the wrongly dropped imx8qm compatible string Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 12:09 ` Krzysztof Kozlowski 2020-11-26 12:09 ` Krzysztof Kozlowski 2020-12-01 1:39 ` Rob Herring 2020-12-01 1:39 ` Rob Herring 2020-12-04 14:38 ` Ulf Hansson 2020-12-04 14:38 ` Ulf Hansson 2020-11-26 10:58 ` [PATCH RESEND v4 02/18] dt-bindings: arm: fsl: add imx8qm boards " Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-12-01 1:39 ` Rob Herring 2020-12-01 1:39 ` Rob Herring 2020-11-26 10:58 ` [PATCH RESEND v4 03/18] dt-bindings: mailbox: mu: add imx8qm support Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-12-01 1:40 ` Rob Herring 2020-12-01 1:40 ` Rob Herring 2020-11-26 10:58 ` [PATCH RESEND v4 04/18] arm64: dts: imx8qxp: add fallback compatible string for scu pd Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:58 ` [PATCH RESEND v4 05/18] arm64: dts: imx8qxp: move scu pd node before scu clock node Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:58 ` [PATCH RESEND v4 06/18] arm64: dts: imx8qxp: orginize dts in subsystems Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:58 ` [PATCH RESEND v4 07/18] arm64: dts: imx8: add lsio lpcg clocks Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng [this message] 2020-11-26 10:58 ` [PATCH RESEND v4 08/18] arm64: dts: imx8: add conn " Dong Aisheng 2020-11-26 10:58 ` [PATCH RESEND v4 09/18] arm64: dts: imx8: add adma " Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:58 ` [PATCH RESEND v4 10/18] arm64: dts: imx8: switch to two cell scu clock binding Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:58 ` [PATCH RESEND v4 11/18] arm64: dts: imx8: switch to new lpcg " Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:58 ` [PATCH RESEND v4 12/18] arm64: dts: imx8qm: add lsio ss support Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:58 ` [PATCH RESEND v4 13/18] arm64: dts: imx8qm: add conn " Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-27 2:11 ` Bough Chen 2020-11-27 2:11 ` Bough Chen 2020-11-26 10:58 ` [PATCH RESEND v4 14/18] arm64: dts: imx8: split adma ss into dma and audio ss Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:58 ` [PATCH RESEND v4 15/18] arm64: dts: imx8qm: add dma ss support Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:58 ` [PATCH RESEND v4 16/18] arm64: dts: imx: add imx8qm common dts file Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:58 ` [PATCH RESEND v4 17/18] arm64: dts: imx: add imx8qm mek support Dong Aisheng 2020-11-26 10:58 ` Dong Aisheng 2020-11-26 10:59 ` [PATCH RESEND v4 18/18] arm64: defconfig: " Dong Aisheng 2020-11-26 10:59 ` Dong Aisheng 2021-02-26 8:33 ` [PATCH RESEND v4 00/18] arm64: dts: imx8: architecture improvement and adding imx8qm support Aisheng Dong 2021-02-26 8:33 ` Aisheng Dong 2021-03-02 9:42 ` Shawn Guo 2021-03-02 9:42 ` Shawn Guo
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