From: "Huang, Sean Z" <sean.z.huang@intel.com>
To: Intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [RFC-v3 06/26] drm/i915/pxp: Add PXP-related registers into allowlist
Date: Tue, 1 Dec 2020 15:33:51 -0800 [thread overview]
Message-ID: <20201201233411.21858-7-sean.z.huang@intel.com> (raw)
In-Reply-To: <20201201233411.21858-1-sean.z.huang@intel.com>
Add several PXP-related reg into allowlist to allow user space
driver to read the those register values.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++
drivers/gpu/drm/i915/intel_uncore.c | 50 ++++++++++++++++++++---------
2 files changed, 41 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3b9ca142539..69758935abb8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12421,4 +12421,10 @@ enum skl_power_gate {
#define TGL_ROOT_DEVICE_SKU_ULX 0x2
#define TGL_ROOT_DEVICE_SKU_ULT 0x4
+/* Registers for allowlist check */
+#define PXP_REG_01_LOWERBOUND _MMIO(0x32260)
+#define PXP_REG_01_UPPERBOUND _MMIO(0x32268)
+#define PXP_REG_02_LOWERBOUND _MMIO(0x32670)
+#define PXP_REG_02_UPPERBOUND _MMIO(0x32678)
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 1c14a07eba7d..8206da8c51a9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1990,16 +1990,34 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
}
static const struct reg_whitelist {
- i915_reg_t offset_ldw;
+ i915_reg_t offset_ldw_lowerbound;
+ i915_reg_t offset_ldw_upperbound;
i915_reg_t offset_udw;
u16 gen_mask;
u8 size;
-} reg_read_whitelist[] = { {
- .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
+} reg_read_whitelist[] = {
+ {
+ .offset_ldw_lowerbound = RING_TIMESTAMP(RENDER_RING_BASE),
+ .offset_ldw_upperbound = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
.gen_mask = INTEL_GEN_MASK(4, 12),
.size = 8
-} };
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_01_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_01_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_02_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_02_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ }
+};
int i915_reg_read_ioctl(struct drm_device *dev,
void *data, struct drm_file *file)
@@ -2012,18 +2030,22 @@ int i915_reg_read_ioctl(struct drm_device *dev,
unsigned int flags;
int remain;
int ret = 0;
+ i915_reg_t offset_ldw;
entry = reg_read_whitelist;
remain = ARRAY_SIZE(reg_read_whitelist);
while (remain) {
- u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
+ u32 entry_offset_lb = i915_mmio_reg_offset(entry->offset_ldw_lowerbound);
+ u32 entry_offset_ub = i915_mmio_reg_offset(entry->offset_ldw_upperbound);
GEM_BUG_ON(!is_power_of_2(entry->size));
GEM_BUG_ON(entry->size > 8);
- GEM_BUG_ON(entry_offset & (entry->size - 1));
+ GEM_BUG_ON(entry_offset_lb & (entry->size - 1));
+ GEM_BUG_ON(entry_offset_ub & (entry->size - 1));
if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
- entry_offset == (reg->offset & -entry->size))
+ entry_offset_lb <= (reg->offset & -entry->size) &&
+ (reg->offset & -entry->size) <= entry_offset_ub)
break;
entry++;
remain--;
@@ -2033,23 +2055,21 @@ int i915_reg_read_ioctl(struct drm_device *dev,
return -EINVAL;
flags = reg->offset & (entry->size - 1);
+ offset_ldw = _MMIO(reg->offset - flags);
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
reg->val = intel_uncore_read64_2x32(uncore,
- entry->offset_ldw,
+ offset_ldw,
entry->offset_udw);
else if (entry->size == 8 && flags == 0)
- reg->val = intel_uncore_read64(uncore,
- entry->offset_ldw);
+ reg->val = intel_uncore_read64(uncore, offset_ldw);
else if (entry->size == 4 && flags == 0)
- reg->val = intel_uncore_read(uncore, entry->offset_ldw);
+ reg->val = intel_uncore_read(uncore, offset_ldw);
else if (entry->size == 2 && flags == 0)
- reg->val = intel_uncore_read16(uncore,
- entry->offset_ldw);
+ reg->val = intel_uncore_read16(uncore, offset_ldw);
else if (entry->size == 1 && flags == 0)
- reg->val = intel_uncore_read8(uncore,
- entry->offset_ldw);
+ reg->val = intel_uncore_read8(uncore, offset_ldw);
else
ret = -EINVAL;
}
--
2.17.1
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next prev parent reply other threads:[~2020-12-01 23:35 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-01 23:33 [Intel-gfx] [RFC-v3 00/26] Introduce Intel PXP component Huang, Sean Z
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 01/26] drm/i915/pxp: " Huang, Sean Z
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 02/26] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 03/26] drm/i915/pxp: Add PXP context for logical hardware states Huang, Sean Z
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 04/26] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 05/26] drm/i915/pxp: Implement ioctl action to set the user space context Huang, Sean Z
2020-12-01 23:33 ` Huang, Sean Z [this message]
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 07/26] drm/i915/pxp: Read register to check hardware session state Huang, Sean Z
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 08/26] drm/i915/pxp: Implement funcs to get/set PXP tag Huang, Sean Z
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 09/26] drm/i915/pxp: Implement ioctl action to reserve session slot Huang, Sean Z
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 10/26] drm/i915/pxp: Implement ioctl action to set session in play Huang, Sean Z
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 11/26] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 12/26] drm/i915/pxp: Implement ioctl action to terminate the session Huang, Sean Z
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 13/26] drm/i915/pxp: Enable ioctl action to query PXP tag Huang, Sean Z
2020-12-01 23:33 ` [Intel-gfx] [RFC-v3 14/26] drm/i915/pxp: Destroy all type0 sessions upon teardown Huang, Sean Z
2020-12-01 23:34 ` [Intel-gfx] [RFC-v3 15/26] drm/i915/pxp: Termiante the session upon app crash Huang, Sean Z
2020-12-01 23:34 ` [Intel-gfx] [RFC-v3 16/26] drm/i915/pxp: Enable PXP power management Huang, Sean Z
2020-12-01 23:34 ` [Intel-gfx] [RFC-v3 17/26] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
2020-12-01 23:34 ` [Intel-gfx] [RFC-v3 18/26] drm/i915/pxp: Implement ioctl action to send TEE commands Huang, Sean Z
2020-12-01 23:34 ` [Intel-gfx] [RFC-v3 19/26] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
2020-12-01 23:34 ` [Intel-gfx] [RFC-v3 20/26] drm/i915/pxp: Add i915 trace logs for PXP operations Huang, Sean Z
2020-12-01 23:34 ` [Intel-gfx] [RFC-v3 21/26] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
2020-12-01 23:34 ` [Intel-gfx] [RFC-v3 22/26] mei: pxp: export pavp client to me client bus Huang, Sean Z
2020-12-01 23:34 ` [Intel-gfx] [RFC-v3 23/26] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
2020-12-01 23:34 ` [Intel-gfx] [RFC-v3 24/26] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
2020-12-01 23:34 ` [Intel-gfx] [RFC-v3 25/26] drm/i915/pxp: Add plane decryption support Huang, Sean Z
2020-12-01 23:34 ` [Intel-gfx] [RFC-v3 26/26] drm/i915/pxp: Enable the PXP ioctl for protected session Huang, Sean Z
2020-12-01 23:42 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Introduce Intel PXP component (rev2) Patchwork
2020-12-01 23:57 [Intel-gfx] [RFC-v3 00/26] Introduce Intel PXP component Huang, Sean Z
2020-12-01 23:57 ` [Intel-gfx] [RFC-v3 06/26] drm/i915/pxp: Add PXP-related registers into allowlist Huang, Sean Z
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