From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: linux-media@vger.kernel.org
Cc: mchehab@kernel.org
Subject: [PATCH 00/38] Support additional CCS PLL features, C-PHY
Date: Wed, 2 Dec 2020 20:06:03 +0200 [thread overview]
Message-ID: <20201202180641.17401-1-sakari.ailus@linux.intel.com> (raw)
Hello everyone,
Here's a set of patches that turn the existing SMIA driver into a MIPI CCS
driver while maintaining SMIA support. A number of bugs in the existing
code are fixed in this set, too.
The changes at this point are primarily focused on dealing with new
mandatory driver features related to PLL configuration (as CCS allows for
much more variation there) and things such as integer conversion from
U16.U16 format instead of float. There are some other new features as well
such as digital gain and support for getting device specific analogue gain
coefficients.
A new feature in CCS is CCS static data which makes it possible to obtain
sensor's capabilities and limits from a file chosen based on sensor
identification. CCS static data is used also for storing MSR registers so
supporting new, CCS compliant devices requires no driver changes.
Also DT bindings are updated accordingly and converted to YAML format.
More information on MIPI CCS can be found here:
<URL:https://www.mipi.org/specifications/camera-command-set>
Comments are welcome.
since the big, big patchset (v2):
- Split into more easily reviewable chunks (this is the first of maybe
three). The cover page describes the entire big set. This set contains
support for additional CCS PLL features as well as making the CCS driver
support them, including trivial dual PLL and C-PHY support --- as the
first upstream sensor driver supporting C-PHY.
- Fix kerneldoc comments in CCS PLL documentation.
Sakari Ailus (38):
ccs-pll: Don't use div_u64 to divide a 32-bit number
ccs-pll: Split limits and PLL configuration into front and back parts
ccs-pll: Use correct VT divisor for calculating VT SYS divisor
ccs-pll: End search if there are no better values available
ccs-pll: Remove parallel bus support
ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY
ccs-pll: Move the flags field down, away from 8-bit fields
ccs-pll: Document the structs in the header as well as the function
ccs-pll: Use the BIT macro
ccs-pll: Begin calculation from OP system clock frequency
ccs-pll: Fix condition for pre-PLL divider lower bound
ccs-pll: Avoid overflow in pre-PLL divisor lower bound search
ccs-pll: Fix comment on check against maximum PLL multiplier
ccs-pll: Fix check for PLL multiplier upper bound
ccs-pll: Use explicit 32-bit unsigned type
ccs-pll: Add support for lane speed model
ccs: Add support for lane speed model
ccs-pll: Add support for decoupled OP domain calculation
ccs-pll: Add support for extended input PLL clock divider
ccs-pll: Support two cycles per pixel on OP domain
ccs-pll: Add support flexible OP PLL pixel clock divider
ccs-pll: Add sanity checks
ccs-pll: Add C-PHY support
ccs-pll: Split off VT subtree calculation
ccs-pll: Check for derating and overrating, support non-derating
sensors
ccs-pll: Better separate OP and VT sub-tree calculation
ccs-pll: Print relevant information on PLL tree
ccs-pll: Rework bounds checks
ccs-pll: Make VT divisors 16-bit
ccs-pll: Fix VT post-PLL divisor calculation
ccs-pll: Separate VT divisor limit calculation from the rest
ccs-pll: Add trivial dual PLL support
ccs: Dual PLL support
ccs-pll: Add support for DDR OP system and pixel clocks
ccs: Add support for DDR OP SYS and OP PIX clocks
ccs: Print written register values
ccs-pll: Print pixel rates
ccs: Add support for obtaining C-PHY configuration from firmware
drivers/media/i2c/ccs-pll.c | 986 +++++++++++++++++--------
drivers/media/i2c/ccs-pll.h | 177 ++++-
drivers/media/i2c/ccs/ccs-core.c | 161 +++-
drivers/media/i2c/ccs/ccs-quirk.c | 5 +-
drivers/media/i2c/ccs/ccs-reg-access.c | 4 +
5 files changed, 974 insertions(+), 359 deletions(-)
--
2.27.0
next reply other threads:[~2020-12-02 18:11 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-02 18:06 Sakari Ailus [this message]
2020-12-02 18:06 ` [PATCH 01/38] ccs-pll: Don't use div_u64 to divide a 32-bit number Sakari Ailus
2020-12-02 18:06 ` [PATCH 02/38] ccs-pll: Split limits and PLL configuration into front and back parts Sakari Ailus
2020-12-02 18:06 ` [PATCH 03/38] ccs-pll: Use correct VT divisor for calculating VT SYS divisor Sakari Ailus
2020-12-02 18:06 ` [PATCH 04/38] ccs-pll: End search if there are no better values available Sakari Ailus
2020-12-02 18:06 ` [PATCH 05/38] ccs-pll: Remove parallel bus support Sakari Ailus
2020-12-02 18:06 ` [PATCH 06/38] ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY Sakari Ailus
2020-12-02 18:06 ` [PATCH 07/38] ccs-pll: Move the flags field down, away from 8-bit fields Sakari Ailus
2020-12-02 18:06 ` [PATCH 08/38] ccs-pll: Document the structs in the header as well as the function Sakari Ailus
2020-12-02 18:06 ` [PATCH 09/38] ccs-pll: Use the BIT macro Sakari Ailus
2020-12-02 18:06 ` [PATCH 10/38] ccs-pll: Begin calculation from OP system clock frequency Sakari Ailus
2020-12-02 18:06 ` [PATCH 11/38] ccs-pll: Fix condition for pre-PLL divider lower bound Sakari Ailus
2020-12-02 18:06 ` [PATCH 12/38] ccs-pll: Avoid overflow in pre-PLL divisor lower bound search Sakari Ailus
2020-12-02 18:06 ` [PATCH 13/38] ccs-pll: Fix comment on check against maximum PLL multiplier Sakari Ailus
2020-12-02 18:06 ` [PATCH 14/38] ccs-pll: Fix check for PLL multiplier upper bound Sakari Ailus
2020-12-02 18:06 ` [PATCH 15/38] ccs-pll: Use explicit 32-bit unsigned type Sakari Ailus
2020-12-02 18:06 ` [PATCH 16/38] ccs-pll: Add support for lane speed model Sakari Ailus
2020-12-02 18:06 ` [PATCH 17/38] ccs: " Sakari Ailus
2020-12-02 18:06 ` [PATCH 18/38] ccs-pll: Add support for decoupled OP domain calculation Sakari Ailus
2020-12-02 18:06 ` [PATCH 19/38] ccs-pll: Add support for extended input PLL clock divider Sakari Ailus
2020-12-02 18:06 ` [PATCH 20/38] ccs-pll: Support two cycles per pixel on OP domain Sakari Ailus
2020-12-02 18:06 ` [PATCH 21/38] ccs-pll: Add support flexible OP PLL pixel clock divider Sakari Ailus
2020-12-02 18:06 ` [PATCH 22/38] ccs-pll: Add sanity checks Sakari Ailus
2020-12-02 18:06 ` [PATCH 23/38] ccs-pll: Add C-PHY support Sakari Ailus
2020-12-02 18:06 ` [PATCH 24/38] ccs-pll: Split off VT subtree calculation Sakari Ailus
2020-12-02 18:06 ` [PATCH 25/38] ccs-pll: Check for derating and overrating, support non-derating sensors Sakari Ailus
2020-12-02 18:06 ` [PATCH 26/38] ccs-pll: Better separate OP and VT sub-tree calculation Sakari Ailus
2020-12-02 18:06 ` [PATCH 27/38] ccs-pll: Print relevant information on PLL tree Sakari Ailus
2020-12-02 18:06 ` [PATCH 28/38] ccs-pll: Rework bounds checks Sakari Ailus
2020-12-02 18:06 ` [PATCH 29/38] ccs-pll: Make VT divisors 16-bit Sakari Ailus
2020-12-02 18:06 ` [PATCH 30/38] ccs-pll: Fix VT post-PLL divisor calculation Sakari Ailus
2020-12-02 18:06 ` [PATCH 31/38] ccs-pll: Separate VT divisor limit calculation from the rest Sakari Ailus
2020-12-02 18:06 ` [PATCH 32/38] ccs-pll: Add trivial dual PLL support Sakari Ailus
2020-12-02 18:06 ` [PATCH 33/38] ccs: Dual " Sakari Ailus
2020-12-02 18:06 ` [PATCH 34/38] ccs-pll: Add support for DDR OP system and pixel clocks Sakari Ailus
2020-12-02 18:06 ` [PATCH 35/38] ccs: Add support for DDR OP SYS and OP PIX clocks Sakari Ailus
2020-12-02 18:06 ` [PATCH 36/38] ccs: Print written register values Sakari Ailus
2020-12-02 18:06 ` [PATCH 37/38] ccs-pll: Print pixel rates Sakari Ailus
2020-12-02 18:06 ` [PATCH 38/38] ccs: Add support for obtaining C-PHY configuration from firmware Sakari Ailus
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