From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: linux-renesas-soc@vger.kernel.org
Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 6/6] WIP: arm64: dts: renesas: falcon: switch to from SCIF0 to HSCIF0
Date: Mon, 28 Dec 2020 12:27:13 +0100 [thread overview]
Message-ID: <20201228112715.14947-7-wsa+renesas@sang-engineering.com> (raw)
In-Reply-To: <20201228112715.14947-1-wsa+renesas@sang-engineering.com>
Mainly for testing the HSCIF0 node. We could make this switch permanent,
but we never did for any other SoC. So, I think this is not to be
applied.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
index 54763c73dc74..e2bbaa7a72e3 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
@@ -14,7 +14,7 @@ / {
compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
aliases {
- serial0 = &scif0;
+ serial0 = &hscif0;
};
chosen {
@@ -352,9 +352,9 @@ mmc_pins: mmc {
power-source = <1800>;
};
- scif0_pins: scif0 {
- groups = "scif0_data", "scif0_ctrl";
- function = "scif0";
+ hscif0_pins: hscif0 {
+ groups = "hscif0_data", "hscif0_ctrl";
+ function = "hscif0";
};
scif_clk_pins: scif_clk {
@@ -369,7 +369,11 @@ &rwdt {
};
&scif0 {
- pinctrl-0 = <&scif0_pins>;
+ status = "disabled";
+};
+
+&hscif0 {
+ pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
--
2.29.2
next prev parent reply other threads:[~2020-12-28 11:28 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-28 11:27 [PATCH 0/6] v3u: add & update (H)SCIF nodes Wolfram Sang
2020-12-28 11:27 ` [PATCH 1/6] arm64: dts: renesas: r8a779a0: add & update SCIF nodes Wolfram Sang
2021-01-05 18:06 ` Geert Uytterhoeven
2021-01-14 20:57 ` Wolfram Sang
2021-01-15 8:00 ` Geert Uytterhoeven
2020-12-28 11:27 ` [PATCH 2/6] arm64: dts: renesas: falcon: add SCIF0 nodes Wolfram Sang
2021-01-05 18:12 ` Geert Uytterhoeven
2021-01-12 11:42 ` Geert Uytterhoeven
2020-12-28 11:27 ` [PATCH 3/6] dt-bindings: serial: renesas,hscif: Add r8a779a0 support Wolfram Sang
2021-01-05 18:19 ` Geert Uytterhoeven
2021-01-08 3:41 ` Rob Herring
2021-01-19 22:16 ` Wolfram Sang
2021-01-20 8:00 ` Greg Kroah-Hartman
2021-01-20 8:02 ` Geert Uytterhoeven
2021-01-20 17:47 ` Greg Kroah-Hartman
2020-12-28 11:27 ` [PATCH 4/6] clk: renesas: r8a779a0: add HSCIF support Wolfram Sang
2021-01-05 18:23 ` Geert Uytterhoeven
2020-12-28 11:27 ` [PATCH 5/6] arm64: dts: renesas: r8a779a0: Add " Wolfram Sang
2021-01-05 18:22 ` Geert Uytterhoeven
2020-12-28 11:27 ` Wolfram Sang [this message]
2021-01-05 16:24 ` [PATCH 6/6] WIP: arm64: dts: renesas: falcon: switch to from SCIF0 to HSCIF0 Geert Uytterhoeven
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