From: Shunsuke Nakamura <nakamura.shun@jp.fujitsu.com> To: john.garry@huawei.com Cc: will@kernel.org, mathieu.poirier@linaro.org, leo.yan@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Shunsuke Nakamura <nakamura.shun@jp.fujitsu.com> Subject: [PATCH v2 1/3] perf vendor events: Add cache refill and DCZVA events Date: Thu, 21 Jan 2021 19:54:23 +0900 [thread overview] Message-ID: <20210121105425.2695843-2-nakamura.shun@jp.fujitsu.com> (raw) In-Reply-To: <20210121105425.2695843-1-nakamura.shun@jp.fujitsu.com> Adds L1 data cache refill prefetch, L2 data cache refill prefetch, and DCZVA instruction events. Signed-off-by: Shunsuke Nakamura <nakamura.shun@jp.fujitsu.com> --- .../perf/pmu-events/arch/arm64/armv8-recommended.json | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json index d0a1986..ee0e67d 100644 --- a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json +++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json @@ -54,6 +54,12 @@ "BriefDescription": "L1D cache invalidate" }, { + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.", + "EventCode": "0x49", + "EventName": "L1D_CACHE_REFILL_PRF", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch." + }, + { "PublicDescription": "Attributable Level 1 data TLB refill, read", "EventCode": "0x4C", "EventName": "L1D_TLB_REFILL_RD", @@ -120,6 +126,12 @@ "BriefDescription": "L2D cache invalidate" }, { + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.", + "EventCode": "0x59", + "EventName": "L2D_CACHE_REFILL_PRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch." + }, + { "PublicDescription": "Attributable Level 2 data or unified TLB refill, read", "EventCode": "0x5c", "EventName": "L2D_TLB_REFILL_RD", @@ -408,6 +420,12 @@ "BriefDescription": "Release consistency operation speculatively executed, Store-Release" }, { + "PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.", + "EventCode": "0x9f", + "EventName": "DCZVA_SPEC", + "BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction." + }, + { "PublicDescription": "Attributable Level 3 data or unified cache access, read", "EventCode": "0xa0", "EventName": "L3D_CACHE_RD", -- 1.8.3.1
WARNING: multiple messages have this Message-ID (diff)
From: Shunsuke Nakamura <nakamura.shun@jp.fujitsu.com> To: john.garry@huawei.com Cc: Shunsuke Nakamura <nakamura.shun@jp.fujitsu.com>, mathieu.poirier@linaro.org, linux-kernel@vger.kernel.org, leo.yan@linaro.org, will@kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/3] perf vendor events: Add cache refill and DCZVA events Date: Thu, 21 Jan 2021 19:54:23 +0900 [thread overview] Message-ID: <20210121105425.2695843-2-nakamura.shun@jp.fujitsu.com> (raw) In-Reply-To: <20210121105425.2695843-1-nakamura.shun@jp.fujitsu.com> Adds L1 data cache refill prefetch, L2 data cache refill prefetch, and DCZVA instruction events. Signed-off-by: Shunsuke Nakamura <nakamura.shun@jp.fujitsu.com> --- .../perf/pmu-events/arch/arm64/armv8-recommended.json | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json index d0a1986..ee0e67d 100644 --- a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json +++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json @@ -54,6 +54,12 @@ "BriefDescription": "L1D cache invalidate" }, { + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.", + "EventCode": "0x49", + "EventName": "L1D_CACHE_REFILL_PRF", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch." + }, + { "PublicDescription": "Attributable Level 1 data TLB refill, read", "EventCode": "0x4C", "EventName": "L1D_TLB_REFILL_RD", @@ -120,6 +126,12 @@ "BriefDescription": "L2D cache invalidate" }, { + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.", + "EventCode": "0x59", + "EventName": "L2D_CACHE_REFILL_PRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch." + }, + { "PublicDescription": "Attributable Level 2 data or unified TLB refill, read", "EventCode": "0x5c", "EventName": "L2D_TLB_REFILL_RD", @@ -408,6 +420,12 @@ "BriefDescription": "Release consistency operation speculatively executed, Store-Release" }, { + "PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.", + "EventCode": "0x9f", + "EventName": "DCZVA_SPEC", + "BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction." + }, + { "PublicDescription": "Attributable Level 3 data or unified cache access, read", "EventCode": "0xa0", "EventName": "L3D_CACHE_RD", -- 1.8.3.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-21 11:18 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-21 10:54 [PATCH v2 0/3] perf vendor events: Support PMU events for A64FX Shunsuke Nakamura 2021-01-21 10:54 ` Shunsuke Nakamura 2021-01-21 10:54 ` Shunsuke Nakamura [this message] 2021-01-21 10:54 ` [PATCH v2 1/3] perf vendor events: Add cache refill and DCZVA events Shunsuke Nakamura 2021-01-21 11:39 ` Shaokun Zhang 2021-01-21 11:39 ` Shaokun Zhang 2021-01-21 17:43 ` John Garry 2021-01-21 17:43 ` John Garry 2021-01-22 8:35 ` nakamura.shun 2021-01-22 8:35 ` nakamura.shun 2021-01-21 10:54 ` [PATCH v2 2/3] perf tools: Fix lexical definition of event name Shunsuke Nakamura 2021-01-21 10:54 ` Shunsuke Nakamura 2021-01-21 10:54 ` [PATCH v2 3/3] perf vendor events: Add Fujitsu A64FX V1.2 pmu event Shunsuke Nakamura 2021-01-21 10:54 ` Shunsuke Nakamura 2021-01-21 17:41 ` John Garry 2021-01-21 17:41 ` John Garry 2021-01-22 8:37 ` nakamura.shun 2021-01-22 8:37 ` nakamura.shun 2021-01-25 12:46 ` John Garry 2021-01-25 12:46 ` John Garry 2021-01-26 8:03 ` nakamura.shun 2021-01-26 8:03 ` nakamura.shun
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