From: <gabriel.fernandez@foss.st.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Maxime Coquelin <mcoquelin.stm32@gmail.com>, Alexandre Torgue <alexandre.torgue@st.com>, Philipp Zabel <p.zabel@pengutronix.de>, Etienne Carriere <etienne.carriere@st.com>, Gabriel Fernandez <gabriel.fernandez@foss.st.com> Cc: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-stm32@st-md-mailman.stormreply.com>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH 10/14] clk: stm32mp1: new compatible for secure RCC support Date: Fri, 22 Jan 2021 11:50:57 +0100 [thread overview] Message-ID: <20210122105101.27374-11-gabriel.fernandez@foss.st.com> (raw) In-Reply-To: <20210122105101.27374-1-gabriel.fernandez@foss.st.com> From: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Platform STM32MP1 can be used in configuration where some clock resources cannot be accessed by Linux kernel when executing in non-secure state of the CPU(s). In such configuration, the RCC clock driver must not register clocks it cannot access. They are expected to be registered from another clock driver such as the SCMI clock driver. This change uses specific compatible string "st,stm32mp1-rcc-secure" to specify RCC clock driver configuration where RCC is secure. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> --- drivers/clk/Kconfig | 10 ++++ drivers/clk/clk-stm32mp1.c | 101 ++++++++++++++++++++++++++++++++++++- 2 files changed, 110 insertions(+), 1 deletion(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 85856cff506c..ee61aec3b490 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -334,6 +334,16 @@ config COMMON_CLK_STM32MP157 help Support for stm32mp157 SoC family clocks +config COMMON_CLK_STM32MP157_SCMI + bool "stm32mp157 Clock diver with Trusted Firmware" + depends on COMMON_CLK_STM32MP157 + select COMMON_CLK_SCMI + select ARM_SCMI_PROTOCOL + default y + help + Support for stm32mp157 SoC family clocks with Trusted Firmware using + SCMI protocol. + config COMMON_CLK_STM32F def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746) help diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 25e3f272344c..132e1dd42dbd 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -2051,11 +2051,61 @@ static const struct clock_config stm32mp1_clock_cfg[] = { _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)), }; +static const u32 stm32mp1_clock_secured[] = { + CK_HSE, + CK_HSI, + CK_CSI, + CK_LSI, + CK_LSE, + PLL1, + PLL2, + PLL1_P, + PLL2_P, + PLL2_Q, + PLL2_R, + CK_MPU, + CK_AXI, + SPI6, + I2C4, + I2C6, + USART1, + RTCAPB, + TZC1, + TZC2, + TZPC, + IWDG1, + BSEC, + STGEN, + GPIOZ, + CRYP1, + HASH1, + RNG1, + BKPSRAM, + RNG1_K, + STGEN_K, + SPI6_K, + I2C4_K, + I2C6_K, + USART1_K, + RTC, +}; + +static bool stm32_check_security(const struct clock_config *cfg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++) + if (cfg->id == stm32mp1_clock_secured[i]) + return true; + return false; +} + struct stm32_rcc_match_data { const struct clock_config *cfg; unsigned int num; unsigned int maxbinding; u32 clear_offset; + bool (*check_security)(const struct clock_config *cfg); }; static struct stm32_rcc_match_data stm32mp1_data = { @@ -2065,11 +2115,23 @@ static struct stm32_rcc_match_data stm32mp1_data = { .clear_offset = RCC_CLR, }; +static struct stm32_rcc_match_data stm32mp1_data_secure = { + .cfg = stm32mp1_clock_cfg, + .num = ARRAY_SIZE(stm32mp1_clock_cfg), + .maxbinding = STM32MP1_LAST_CLK, + .clear_offset = RCC_CLR, + .check_security = &stm32_check_security +}; + static const struct of_device_id stm32mp1_match_data[] = { { .compatible = "st,stm32mp1-rcc", .data = &stm32mp1_data, }, + { + .compatible = "st,stm32mp1-rcc-secure", + .data = &stm32mp1_data_secure, + }, { } }; MODULE_DEVICE_TABLE(of, stm32mp1_match_data); @@ -2229,6 +2291,9 @@ static int stm32_rcc_clock_init(struct device *dev, void __iomem *base, hws[n] = ERR_PTR(-ENOENT); for (n = 0; n < data->num; n++) { + if (data->check_security && data->check_security(&data->cfg[n])) + continue; + err = stm32_register_hw_clk(dev, clk_data, base, &rlock, &data->cfg[n]); if (err) { @@ -2296,11 +2361,45 @@ static int stm32mp1_rcc_init(struct device *dev) return ret; } +static int get_clock_deps(struct device *dev) +{ + static const char * const clock_deps_name[] = { + "hsi", "hse", "csi", "lsi", "lse", + }; + size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name); + struct clk **clk_deps; + int i; + + clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL); + if (!clk_deps) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) { + struct clk *clk = of_clk_get_by_name(dev_of_node(dev), + clock_deps_name[i]); + + if (IS_ERR(clk)) { + if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT) + return PTR_ERR(clk); + } else { + /* Device gets a reference count on the clock */ + clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk)); + clk_put(clk); + } + } + + return 0; +} + static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + int ret = get_clock_deps(dev); + + if (!ret) + ret = stm32mp1_rcc_init(dev); - return stm32mp1_rcc_init(dev); + return ret; } static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: <gabriel.fernandez@foss.st.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Maxime Coquelin <mcoquelin.stm32@gmail.com>, Alexandre Torgue <alexandre.torgue@st.com>, Philipp Zabel <p.zabel@pengutronix.de>, Etienne Carriere <etienne.carriere@st.com>, Gabriel Fernandez <gabriel.fernandez@foss.st.com> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 10/14] clk: stm32mp1: new compatible for secure RCC support Date: Fri, 22 Jan 2021 11:50:57 +0100 [thread overview] Message-ID: <20210122105101.27374-11-gabriel.fernandez@foss.st.com> (raw) In-Reply-To: <20210122105101.27374-1-gabriel.fernandez@foss.st.com> From: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Platform STM32MP1 can be used in configuration where some clock resources cannot be accessed by Linux kernel when executing in non-secure state of the CPU(s). In such configuration, the RCC clock driver must not register clocks it cannot access. They are expected to be registered from another clock driver such as the SCMI clock driver. This change uses specific compatible string "st,stm32mp1-rcc-secure" to specify RCC clock driver configuration where RCC is secure. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> --- drivers/clk/Kconfig | 10 ++++ drivers/clk/clk-stm32mp1.c | 101 ++++++++++++++++++++++++++++++++++++- 2 files changed, 110 insertions(+), 1 deletion(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 85856cff506c..ee61aec3b490 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -334,6 +334,16 @@ config COMMON_CLK_STM32MP157 help Support for stm32mp157 SoC family clocks +config COMMON_CLK_STM32MP157_SCMI + bool "stm32mp157 Clock diver with Trusted Firmware" + depends on COMMON_CLK_STM32MP157 + select COMMON_CLK_SCMI + select ARM_SCMI_PROTOCOL + default y + help + Support for stm32mp157 SoC family clocks with Trusted Firmware using + SCMI protocol. + config COMMON_CLK_STM32F def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746) help diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 25e3f272344c..132e1dd42dbd 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -2051,11 +2051,61 @@ static const struct clock_config stm32mp1_clock_cfg[] = { _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)), }; +static const u32 stm32mp1_clock_secured[] = { + CK_HSE, + CK_HSI, + CK_CSI, + CK_LSI, + CK_LSE, + PLL1, + PLL2, + PLL1_P, + PLL2_P, + PLL2_Q, + PLL2_R, + CK_MPU, + CK_AXI, + SPI6, + I2C4, + I2C6, + USART1, + RTCAPB, + TZC1, + TZC2, + TZPC, + IWDG1, + BSEC, + STGEN, + GPIOZ, + CRYP1, + HASH1, + RNG1, + BKPSRAM, + RNG1_K, + STGEN_K, + SPI6_K, + I2C4_K, + I2C6_K, + USART1_K, + RTC, +}; + +static bool stm32_check_security(const struct clock_config *cfg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++) + if (cfg->id == stm32mp1_clock_secured[i]) + return true; + return false; +} + struct stm32_rcc_match_data { const struct clock_config *cfg; unsigned int num; unsigned int maxbinding; u32 clear_offset; + bool (*check_security)(const struct clock_config *cfg); }; static struct stm32_rcc_match_data stm32mp1_data = { @@ -2065,11 +2115,23 @@ static struct stm32_rcc_match_data stm32mp1_data = { .clear_offset = RCC_CLR, }; +static struct stm32_rcc_match_data stm32mp1_data_secure = { + .cfg = stm32mp1_clock_cfg, + .num = ARRAY_SIZE(stm32mp1_clock_cfg), + .maxbinding = STM32MP1_LAST_CLK, + .clear_offset = RCC_CLR, + .check_security = &stm32_check_security +}; + static const struct of_device_id stm32mp1_match_data[] = { { .compatible = "st,stm32mp1-rcc", .data = &stm32mp1_data, }, + { + .compatible = "st,stm32mp1-rcc-secure", + .data = &stm32mp1_data_secure, + }, { } }; MODULE_DEVICE_TABLE(of, stm32mp1_match_data); @@ -2229,6 +2291,9 @@ static int stm32_rcc_clock_init(struct device *dev, void __iomem *base, hws[n] = ERR_PTR(-ENOENT); for (n = 0; n < data->num; n++) { + if (data->check_security && data->check_security(&data->cfg[n])) + continue; + err = stm32_register_hw_clk(dev, clk_data, base, &rlock, &data->cfg[n]); if (err) { @@ -2296,11 +2361,45 @@ static int stm32mp1_rcc_init(struct device *dev) return ret; } +static int get_clock_deps(struct device *dev) +{ + static const char * const clock_deps_name[] = { + "hsi", "hse", "csi", "lsi", "lse", + }; + size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name); + struct clk **clk_deps; + int i; + + clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL); + if (!clk_deps) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) { + struct clk *clk = of_clk_get_by_name(dev_of_node(dev), + clock_deps_name[i]); + + if (IS_ERR(clk)) { + if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT) + return PTR_ERR(clk); + } else { + /* Device gets a reference count on the clock */ + clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk)); + clk_put(clk); + } + } + + return 0; +} + static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + int ret = get_clock_deps(dev); + + if (!ret) + ret = stm32mp1_rcc_init(dev); - return stm32mp1_rcc_init(dev); + return ret; } static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev) -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-22 11:05 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-22 10:50 [PATCH 00/14] Introduce STM32MP1 RCC in secured mode gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez 2021-01-22 10:50 ` [PATCH 01/14] clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez 2021-01-22 10:50 ` [PATCH 02/14] clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' " gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez 2021-01-22 10:50 ` [PATCH 03/14] clk: stm32mp1: remove intermediate pll clocks gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez 2021-01-22 10:50 ` [PATCH 04/14] clk: stm32mp1: convert to module driver gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez 2021-01-22 10:50 ` [PATCH 05/14] clk: stm32mp1: move RCC reset controller into RCC clock driver gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez 2021-01-22 10:50 ` [PATCH 06/14] reset: stm32mp1: remove stm32mp1 reset gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez 2021-01-22 10:50 ` [PATCH 07/14] dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez 2021-01-22 10:50 ` [PATCH 08/14] dt-bindings: reset: add IDs for SCMI reset domains " gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez 2021-01-22 10:50 ` [PATCH 09/14] dt-bindings: reset: add MCU HOLD BOOT ID " gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez [this message] 2021-01-22 10:50 ` [PATCH 10/14] clk: stm32mp1: new compatible for secure RCC support gabriel.fernandez 2021-01-22 10:50 ` [PATCH 11/14] ARM: dts: stm32: define SCMI resources on stm32mp15 gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez 2021-01-22 10:50 ` [PATCH 12/14] ARM: dts: stm32: move clocks/resets to SCMI resources for stm32mp15 gabriel.fernandez 2021-01-22 10:50 ` gabriel.fernandez 2021-01-22 10:51 ` [PATCH 13/14] dt-bindings: clock: stm32mp1 new compatible for secure rcc gabriel.fernandez 2021-01-22 10:51 ` gabriel.fernandez 2021-01-22 14:00 ` Rob Herring 2021-01-22 14:00 ` Rob Herring 2021-01-25 13:22 ` gabriel.fernandez 2021-01-25 13:22 ` gabriel.fernandez 2021-01-22 10:51 ` [PATCH 14/14] ARM: dts: stm32: introduce basic boot include on stm32mp15x board gabriel.fernandez 2021-01-22 10:51 ` gabriel.fernandez
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