From: Mathieu Poirier <mathieu.poirier@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 16/31] coresight: etm4x: Check for Software Lock Date: Mon, 1 Feb 2021 11:13:36 -0700 [thread overview] Message-ID: <20210201181351.1475223-17-mathieu.poirier@linaro.org> (raw) In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> From: Suzuki K Poulose <suzuki.poulose@arm.com> The Software lock is not implemented for system instructions based accesses. So, skip the lock register access in such cases. Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210110224850.1880240-15-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- .../coresight/coresight-etm4x-core.c | 40 ++++++++++++------- 1 file changed, 26 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 04ec13ae22d0..f095ab9949d9 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -133,6 +133,21 @@ static void etm4_os_lock(struct etmv4_drvdata *drvdata) isb(); } +static void etm4_cs_lock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + /* Software Lock is only accessible via memory mapped interface */ + if (csa->io_mem) + CS_LOCK(csa->base); +} + +static void etm4_cs_unlock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + if (csa->io_mem) + CS_UNLOCK(csa->base); +} + static bool etm4_arch_supported(u8 arch) { /* Mask out the minor version number */ @@ -263,7 +278,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) struct device *etm_dev = &csdev->dev; struct csdev_access *csa = &csdev->access; - CS_UNLOCK(drvdata->base); + + etm4_cs_unlock(drvdata, csa); etm4_enable_arch_specific(drvdata); etm4_os_unlock(drvdata); @@ -366,7 +382,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) isb(); done: - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n", drvdata->cpu, rc); @@ -623,7 +639,7 @@ static void etm4_disable_hw(void *info) struct csdev_access *csa = &csdev->access; int i; - CS_UNLOCK(drvdata->base); + etm4_cs_unlock(drvdata, csa); etm4_disable_arch_specific(drvdata); if (!drvdata->skip_power_up) { @@ -665,8 +681,7 @@ static void etm4_disable_hw(void *info) } coresight_disclaim_device_unlocked(csdev); - - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); dev_dbg(&drvdata->csdev->dev, "cpu: %d disable smp call done\n", drvdata->cpu); @@ -776,8 +791,7 @@ static void etm4_init_arch_data(void *info) /* Make sure all registers are accessible */ etm4_os_unlock_csa(drvdata, csa); - - CS_UNLOCK(drvdata->base); + etm4_cs_unlock(drvdata, csa); /* find all capabilities of the tracing unit */ etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); @@ -942,7 +956,7 @@ static void etm4_init_arch_data(void *info) drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); /* NUMCNTR, bits[30:28] number of counters available for tracing */ drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); } /* Set ELx trace filter access in the TRCVICTLR register */ @@ -1323,8 +1337,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) dsb(sy); isb(); - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); /* Lock the OS lock to disable trace and external debugger access */ etm4_os_lock(drvdata); @@ -1437,7 +1450,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), TRCPDCR); out: - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); return ret; } @@ -1448,8 +1461,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base); struct csdev_access *csa = &tmp_csa; - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR); @@ -1534,7 +1546,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) /* Unlock the OS lock to re-enable trace and external debug access */ etm4_os_unlock(drvdata); - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); } static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 16/31] coresight: etm4x: Check for Software Lock Date: Mon, 1 Feb 2021 11:13:36 -0700 [thread overview] Message-ID: <20210201181351.1475223-17-mathieu.poirier@linaro.org> (raw) In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> From: Suzuki K Poulose <suzuki.poulose@arm.com> The Software lock is not implemented for system instructions based accesses. So, skip the lock register access in such cases. Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210110224850.1880240-15-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- .../coresight/coresight-etm4x-core.c | 40 ++++++++++++------- 1 file changed, 26 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 04ec13ae22d0..f095ab9949d9 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -133,6 +133,21 @@ static void etm4_os_lock(struct etmv4_drvdata *drvdata) isb(); } +static void etm4_cs_lock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + /* Software Lock is only accessible via memory mapped interface */ + if (csa->io_mem) + CS_LOCK(csa->base); +} + +static void etm4_cs_unlock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + if (csa->io_mem) + CS_UNLOCK(csa->base); +} + static bool etm4_arch_supported(u8 arch) { /* Mask out the minor version number */ @@ -263,7 +278,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) struct device *etm_dev = &csdev->dev; struct csdev_access *csa = &csdev->access; - CS_UNLOCK(drvdata->base); + + etm4_cs_unlock(drvdata, csa); etm4_enable_arch_specific(drvdata); etm4_os_unlock(drvdata); @@ -366,7 +382,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) isb(); done: - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n", drvdata->cpu, rc); @@ -623,7 +639,7 @@ static void etm4_disable_hw(void *info) struct csdev_access *csa = &csdev->access; int i; - CS_UNLOCK(drvdata->base); + etm4_cs_unlock(drvdata, csa); etm4_disable_arch_specific(drvdata); if (!drvdata->skip_power_up) { @@ -665,8 +681,7 @@ static void etm4_disable_hw(void *info) } coresight_disclaim_device_unlocked(csdev); - - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); dev_dbg(&drvdata->csdev->dev, "cpu: %d disable smp call done\n", drvdata->cpu); @@ -776,8 +791,7 @@ static void etm4_init_arch_data(void *info) /* Make sure all registers are accessible */ etm4_os_unlock_csa(drvdata, csa); - - CS_UNLOCK(drvdata->base); + etm4_cs_unlock(drvdata, csa); /* find all capabilities of the tracing unit */ etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); @@ -942,7 +956,7 @@ static void etm4_init_arch_data(void *info) drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); /* NUMCNTR, bits[30:28] number of counters available for tracing */ drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); } /* Set ELx trace filter access in the TRCVICTLR register */ @@ -1323,8 +1337,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) dsb(sy); isb(); - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); /* Lock the OS lock to disable trace and external debugger access */ etm4_os_lock(drvdata); @@ -1437,7 +1450,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), TRCPDCR); out: - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); return ret; } @@ -1448,8 +1461,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base); struct csdev_access *csa = &tmp_csa; - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR); @@ -1534,7 +1546,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) /* Unlock the OS lock to re-enable trace and external debug access */ etm4_os_unlock(drvdata); - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); } static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-02-01 18:31 UTC|newest] Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-01 18:13 [PATCH 00/31] coresight: Patches for v5.12 Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 01/31] coresight: cti: Reduce scope for the variable 'cs_fwnode' in cti_plat_create_connection() Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 02/31] coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75 Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 03/31] coresight: etm4x: Handle access to TRCSSPCICRn Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 04/31] coresight: etm4x: Skip accessing TRCPDCR in save/restore Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 05/31] coresight: Introduce device access abstraction Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 06/31] coresight: tpiu: Prepare for using coresight " Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 07/31] coresight: Convert coresight_timeout to use " Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 08/31] coresight: Convert claim/disclaim operations to use access wrappers Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 09/31] coresight: etm4x: Always read the registers on the host CPU Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 10/31] coresight: etm4x: Convert all register accesses Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 11/31] coresight: etm4x: Make offset available for sysfs attributes Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 12/31] coresight: etm4x: Add commentary on the registers Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 13/31] coresight: etm4x: Add sysreg access helpers Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 14/31] coresight: etm4x: Hide sysfs attributes for unavailable registers Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 15/31] coresight: etm4x: Define DEVARCH register fields Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier [this message] 2021-02-01 18:13 ` [PATCH 16/31] coresight: etm4x: Check for Software Lock Mathieu Poirier 2021-02-01 18:13 ` [PATCH 17/31] coresight: etm4x: Cleanup secure exception level masks Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 18/31] coresight: etm4x: Clean up " Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 19/31] coresight: etm4x: Handle ETM architecture version Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 20/31] coresight: etm4x: Detect access early on the target CPU Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 21/31] coresight: etm4x: Use TRCDEVARCH for component discovery Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 22/31] coresight: etm4x: Expose trcdevarch via sysfs Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 23/31] coresight: etm4x: Add necessary synchronization for sysreg access Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 24/31] coresight: etm4x: Detect system instructions support Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 25/31] coresight: etm4x: Refactor probing routine Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 26/31] coresight: etm4x: Run arch feature detection on the CPU Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 27/31] coresight: etm4x: Add support for sysreg only devices Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 28/31] dts: bindings: coresight: ETM system register access only units Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 29/31] arm64: Add TRFCR_ELx definitions Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 30/31] coresight: Add support for v8.4 SelfHosted tracing Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-01 18:13 ` [PATCH 31/31] coresight: etm4x: Handle accesses to TRCSTALLCTLR Mathieu Poirier 2021-02-01 18:13 ` Mathieu Poirier 2021-02-04 16:01 ` [PATCH 00/31] coresight: Patches for v5.12 Greg KH 2021-02-04 16:01 ` Greg KH
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