From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> To: intel-gfx@lists.freedesktop.org Cc: uma.shankar@intel.com, dri-devel@lists.freedesktop.org Subject: [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 Date: Thu, 4 Feb 2021 12:18:40 +0530 [thread overview] Message-ID: <20210204064842.11595-2-ankit.k.nautiyal@intel.com> (raw) In-Reply-To: <20210204064842.11595-1-ankit.k.nautiyal@intel.com> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E. Do not read the registers if DPCD rev < 1.4. Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868 Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8c12d5375607..2b83f0f433a2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) struct drm_i915_private *i915 = dp_to_i915(intel_dp); /* Clear the cached register set to avoid using stale values */ - memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) + return; + if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, intel_dp->pcon_dsc_dpcd, sizeof(intel_dp->pcon_dsc_dpcd)) < 0) -- 2.29.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 Date: Thu, 4 Feb 2021 12:18:40 +0530 [thread overview] Message-ID: <20210204064842.11595-2-ankit.k.nautiyal@intel.com> (raw) In-Reply-To: <20210204064842.11595-1-ankit.k.nautiyal@intel.com> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E. Do not read the registers if DPCD rev < 1.4. Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868 Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8c12d5375607..2b83f0f433a2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) struct drm_i915_private *i915 = dp_to_i915(intel_dp); /* Clear the cached register set to avoid using stale values */ - memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) + return; + if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, intel_dp->pcon_dsc_dpcd, sizeof(intel_dp->pcon_dsc_dpcd)) < 0) -- 2.29.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-02-04 6:58 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-04 6:48 [PATCH 0/3] HDMI2.1 PCON Misc Fixes Ankit Nautiyal 2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal 2021-02-04 6:48 ` Ankit Nautiyal [this message] 2021-02-04 6:48 ` [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 Ankit Nautiyal 2021-02-05 19:58 ` Ville Syrjälä 2021-02-05 19:58 ` [Intel-gfx] " Ville Syrjälä 2021-02-05 20:07 ` Navare, Manasi 2021-02-05 20:07 ` Navare, Manasi 2021-02-05 20:06 ` Ville Syrjälä 2021-02-05 20:06 ` Ville Syrjälä 2021-02-05 20:22 ` Navare, Manasi 2021-02-05 20:22 ` Navare, Manasi 2021-02-08 11:15 ` Jani Nikula 2021-02-08 11:15 ` [Intel-gfx] " Jani Nikula 2021-02-08 11:44 ` Nautiyal, Ankit K 2021-02-08 11:44 ` [Intel-gfx] " Nautiyal, Ankit K 2021-03-09 4:28 ` Nautiyal, Ankit K 2021-03-09 4:28 ` [Intel-gfx] " Nautiyal, Ankit K 2021-02-04 6:48 ` [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON Ankit Nautiyal 2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal 2021-02-05 20:00 ` Ville Syrjälä 2021-02-05 20:00 ` [Intel-gfx] " Ville Syrjälä 2021-02-11 6:56 ` Nautiyal, Ankit K 2021-02-11 6:56 ` [Intel-gfx] " Nautiyal, Ankit K 2021-02-11 6:43 ` [PATCH v2 " Ankit Nautiyal 2021-02-11 6:43 ` [Intel-gfx] " Ankit Nautiyal 2021-02-04 6:48 ` [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms Ankit Nautiyal 2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal 2021-02-05 20:01 ` Ville Syrjälä 2021-02-05 20:01 ` [Intel-gfx] " Ville Syrjälä 2021-02-04 7:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDMI2.1 PCON Misc Fixes Patchwork 2021-02-04 8:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-02-04 9:38 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-02-11 7:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDMI2.1 PCON Misc Fixes (rev2) Patchwork 2021-02-11 8:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-02-11 13:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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