From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: gregkh@linuxfoundation.org
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org,
"José Roberto de Souza" <jose.souza@intel.com>,
"Clinton Taylor" <clinton.a.taylor@intel.com>,
"Imre Deak" <imre.deak@intel.com>
Subject: [PATCH stable-5.10 1/2] drm/i915: Fix ICL MG PHY vswing handling
Date: Mon, 8 Feb 2021 19:53:40 +0200 [thread overview]
Message-ID: <20210208175341.8695-1-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <16127808794868@kroah.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
commit a2a5f5628e5494ca9353f761f7fe783dfa82fb9a upstream.
The MH PHY vswing table does have all the entries these days. Get
rid of the old hacks in the code which claim otherwise.
This hack was totally bogus anyway. The correct way to handle the
lack of those two entries would have been to declare our max
vswing and pre-emph to both be level 2.
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Fixes: 9f7ffa297978 ("drm/i915/tc/icl: Update TC vswing tables")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201207203512.1718-1-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit 5ec346476e795089b7dac8ab9dcee30c8d80ad84)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
(cherry picked from commit a2a5f5628e5494ca9353f761f7fe783dfa82fb9a)
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3f2bbd9370a8..51f4f4374dea 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2605,12 +2605,11 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
&n_entries);
- /* The table does not have values for level 3 and level 9. */
- if (level >= n_entries || level == 3 || level == 9) {
+ if (level >= n_entries) {
drm_dbg_kms(&dev_priv->drm,
"DDI translation not found for level %d. Using %d instead.",
- level, n_entries - 2);
- level = n_entries - 2;
+ level, n_entries - 1);
+ level = n_entries - 1;
}
/* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
--
2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: gregkh@linuxfoundation.org
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org
Subject: [Intel-gfx] [PATCH stable-5.10 1/2] drm/i915: Fix ICL MG PHY vswing handling
Date: Mon, 8 Feb 2021 19:53:40 +0200 [thread overview]
Message-ID: <20210208175341.8695-1-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <16127808794868@kroah.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
commit a2a5f5628e5494ca9353f761f7fe783dfa82fb9a upstream.
The MH PHY vswing table does have all the entries these days. Get
rid of the old hacks in the code which claim otherwise.
This hack was totally bogus anyway. The correct way to handle the
lack of those two entries would have been to declare our max
vswing and pre-emph to both be level 2.
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Fixes: 9f7ffa297978 ("drm/i915/tc/icl: Update TC vswing tables")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201207203512.1718-1-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit 5ec346476e795089b7dac8ab9dcee30c8d80ad84)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
(cherry picked from commit a2a5f5628e5494ca9353f761f7fe783dfa82fb9a)
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3f2bbd9370a8..51f4f4374dea 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2605,12 +2605,11 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
&n_entries);
- /* The table does not have values for level 3 and level 9. */
- if (level >= n_entries || level == 3 || level == 9) {
+ if (level >= n_entries) {
drm_dbg_kms(&dev_priv->drm,
"DDI translation not found for level %d. Using %d instead.",
- level, n_entries - 2);
- level = n_entries - 2;
+ level, n_entries - 1);
+ level = n_entries - 1;
}
/* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
--
2.26.2
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next prev parent reply other threads:[~2021-02-08 17:58 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-08 10:41 FAILED: patch "[PATCH] drm/i915: Skip vswing programming for TBT" failed to apply to 5.10-stable tree gregkh
2021-02-08 17:53 ` Ville Syrjala [this message]
2021-02-08 17:53 ` [Intel-gfx] [PATCH stable-5.10 1/2] drm/i915: Fix ICL MG PHY vswing handling Ville Syrjala
2021-02-08 17:53 ` [PATCH stable-5.10 2/2] drm/i915: Skip vswing programming for TBT Ville Syrjala
2021-02-08 17:53 ` [Intel-gfx] " Ville Syrjala
2021-02-11 14:18 ` Greg KH
2021-02-11 14:18 ` [Intel-gfx] " Greg KH
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