From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Fredrik Noring" <noring@nocrew.org>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Laurent Vivier" <laurent@vivier.eu>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Thomas Huth" <thuth@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Maciej W. Rozycki" <macro@orcam.me.uk>
Subject: [RFC PATCH 14/42] target/mips/tx79: Salvage instructions description comment
Date: Sun, 14 Feb 2021 18:58:44 +0100 [thread overview]
Message-ID: <20210214175912.732946-15-f4bug@amsat.org> (raw)
In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org>
This comment describing the tx79 opcodes is helpful. As we
will implement these instructions in tx79_translate.c, move
the comment there.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 160 -----------------------------
target/mips/tx79_translate.c | 188 +++++++++++++++++++++++++++++++++++
2 files changed, 188 insertions(+), 160 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 22d106405c6..109f7f80f3d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1743,166 +1743,6 @@ enum {
};
/*
- * Overview of the TX79-specific instruction set
- * =============================================
- *
- * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
- * are only used by the specific quadword (128-bit) LQ/SQ load/store
- * instructions and certain multimedia instructions (MMIs). These MMIs
- * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
- * or sixteen 8-bit paths.
- *
- * Reference:
- *
- * The Toshiba TX System RISC TX79 Core Architecture manual,
- * https://wiki.qemu.org/File:C790.pdf
- *
- * Three-Operand Multiply and Multiply-Add (4 instructions)
- * --------------------------------------------------------
- * MADD [rd,] rs, rt Multiply/Add
- * MADDU [rd,] rs, rt Multiply/Add Unsigned
- * MULT [rd,] rs, rt Multiply (3-operand)
- * MULTU [rd,] rs, rt Multiply Unsigned (3-operand)
- *
- * Multiply Instructions for Pipeline 1 (10 instructions)
- * ------------------------------------------------------
- * MULT1 [rd,] rs, rt Multiply Pipeline 1
- * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1
- * DIV1 rs, rt Divide Pipeline 1
- * DIVU1 rs, rt Divide Unsigned Pipeline 1
- * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1
- * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1
- * MFHI1 rd Move From HI1 Register
- * MFLO1 rd Move From LO1 Register
- * MTHI1 rs Move To HI1 Register
- * MTLO1 rs Move To LO1 Register
- *
- * Arithmetic (19 instructions)
- * ----------------------------
- * PADDB rd, rs, rt Parallel Add Byte
- * PSUBB rd, rs, rt Parallel Subtract Byte
- * PADDH rd, rs, rt Parallel Add Halfword
- * PSUBH rd, rs, rt Parallel Subtract Halfword
- * PADDW rd, rs, rt Parallel Add Word
- * PSUBW rd, rs, rt Parallel Subtract Word
- * PADSBH rd, rs, rt Parallel Add/Subtract Halfword
- * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte
- * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte
- * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword
- * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword
- * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word
- * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word
- * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte
- * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte
- * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword
- * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword
- * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word
- * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word
- *
- * Min/Max (4 instructions)
- * ------------------------
- * PMAXH rd, rs, rt Parallel Maximum Halfword
- * PMINH rd, rs, rt Parallel Minimum Halfword
- * PMAXW rd, rs, rt Parallel Maximum Word
- * PMINW rd, rs, rt Parallel Minimum Word
- *
- * Absolute (2 instructions)
- * -------------------------
- * PABSH rd, rt Parallel Absolute Halfword
- * PABSW rd, rt Parallel Absolute Word
- *
- * Logical (4 instructions)
- * ------------------------
- * PAND rd, rs, rt Parallel AND
- * POR rd, rs, rt Parallel OR
- * PXOR rd, rs, rt Parallel XOR
- * PNOR rd, rs, rt Parallel NOR
- *
- * Shift (9 instructions)
- * ----------------------
- * PSLLH rd, rt, sa Parallel Shift Left Logical Halfword
- * PSRLH rd, rt, sa Parallel Shift Right Logical Halfword
- * PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword
- * PSLLW rd, rt, sa Parallel Shift Left Logical Word
- * PSRLW rd, rt, sa Parallel Shift Right Logical Word
- * PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word
- * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word
- * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word
- * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word
- *
- * Compare (6 instructions)
- * ------------------------
- * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte
- * PCEQB rd, rs, rt Parallel Compare for Equal Byte
- * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword
- * PCEQH rd, rs, rt Parallel Compare for Equal Halfword
- * PCGTW rd, rs, rt Parallel Compare for Greater Than Word
- * PCEQW rd, rs, rt Parallel Compare for Equal Word
- *
- * LZC (1 instruction)
- * -------------------
- * PLZCW rd, rs Parallel Leading Zero or One Count Word
- *
- * Quadword Load and Store (2 instructions)
- * ----------------------------------------
- * LQ rt, offset(base) Load Quadword
- * SQ rt, offset(base) Store Quadword
- *
- * Multiply and Divide (19 instructions)
- * -------------------------------------
- * PMULTW rd, rs, rt Parallel Multiply Word
- * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word
- * PDIVW rs, rt Parallel Divide Word
- * PDIVUW rs, rt Parallel Divide Unsigned Word
- * PMADDW rd, rs, rt Parallel Multiply-Add Word
- * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word
- * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word
- * PMULTH rd, rs, rt Parallel Multiply Halfword
- * PMADDH rd, rs, rt Parallel Multiply-Add Halfword
- * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword
- * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword
- * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword
- * PDIVBW rs, rt Parallel Divide Broadcast Word
- * PMFHI rd Parallel Move From HI Register
- * PMFLO rd Parallel Move From LO Register
- * PMTHI rs Parallel Move To HI Register
- * PMTLO rs Parallel Move To LO Register
- * PMFHL rd Parallel Move From HI/LO Register
- * PMTHL rs Parallel Move To HI/LO Register
- *
- * Pack/Extend (11 instructions)
- * -----------------------------
- * PPAC5 rd, rt Parallel Pack to 5 bits
- * PPACB rd, rs, rt Parallel Pack to Byte
- * PPACH rd, rs, rt Parallel Pack to Halfword
- * PPACW rd, rs, rt Parallel Pack to Word
- * PEXT5 rd, rt Parallel Extend Upper from 5 bits
- * PEXTUB rd, rs, rt Parallel Extend Upper from Byte
- * PEXTLB rd, rs, rt Parallel Extend Lower from Byte
- * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword
- * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword
- * PEXTUW rd, rs, rt Parallel Extend Upper from Word
- * PEXTLW rd, rs, rt Parallel Extend Lower from Word
- *
- * Others (16 instructions)
- * ------------------------
- * PCPYH rd, rt Parallel Copy Halfword
- * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword
- * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword
- * PREVH rd, rt Parallel Reverse Halfword
- * PINTH rd, rs, rt Parallel Interleave Halfword
- * PINTEH rd, rs, rt Parallel Interleave Even Halfword
- * PEXEH rd, rt Parallel Exchange Even Halfword
- * PEXCH rd, rt Parallel Exchange Center Halfword
- * PEXEW rd, rt Parallel Exchange Even Word
- * PEXCW rd, rt Parallel Exchange Center Word
- * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable
- * MFSA rd Move from Shift Amount Register
- * MTSA rs Move to Shift Amount Register
- * MTSAB rs, immediate Move Byte Count to Shift Amount Register
- * MTSAH rs, immediate Move Halfword Count to Shift Amount Register
- * PROT3W rd, rt Parallel Rotate 3 Words
- *
* MMI (MultiMedia Instruction) encodings
* ======================================
*
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index de09bb0d314..243a81c3c5e 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -14,6 +14,22 @@
/* Include the auto-generated decoder. */
#include "decode-tx79.c.inc"
+/*
+ * Overview of the TX79-specific instruction set
+ * =============================================
+ *
+ * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
+ * are only used by the specific quadword (128-bit) LQ/SQ load/store
+ * instructions and certain multimedia instructions (MMIs). These MMIs
+ * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
+ * or sixteen 8-bit paths.
+ *
+ * Reference:
+ *
+ * The Toshiba TX System RISC TX79 Core Architecture manual,
+ * https://wiki.qemu.org/File:C790.pdf
+ */
+
bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
{
if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) {
@@ -22,6 +38,30 @@ bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
return false;
}
+/*
+ * Three-Operand Multiply and Multiply-Add (4 instructions)
+ * --------------------------------------------------------
+ * MADD [rd,] rs, rt Multiply/Add
+ * MADDU [rd,] rs, rt Multiply/Add Unsigned
+ * MULT [rd,] rs, rt Multiply (3-operand)
+ * MULTU [rd,] rs, rt Multiply Unsigned (3-operand)
+ */
+
+/*
+ * Multiply Instructions for Pipeline 1 (10 instructions)
+ * ------------------------------------------------------
+ * MULT1 [rd,] rs, rt Multiply Pipeline 1
+ * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1
+ * DIV1 rs, rt Divide Pipeline 1
+ * DIVU1 rs, rt Divide Unsigned Pipeline 1
+ * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1
+ * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1
+ * MFHI1 rd Move From HI1 Register
+ * MFLO1 rd Move From LO1 Register
+ * MTHI1 rs Move To HI1 Register
+ * MTLO1 rs Move To LO1 Register
+ */
+
static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a)
{
gen_store_gpr(cpu_HI[1], a->rd);
@@ -50,6 +90,154 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
return true;
}
+/*
+ * Arithmetic (19 instructions)
+ * ----------------------------
+ * PADDB rd, rs, rt Parallel Add Byte
+ * PSUBB rd, rs, rt Parallel Subtract Byte
+ * PADDH rd, rs, rt Parallel Add Halfword
+ * PSUBH rd, rs, rt Parallel Subtract Halfword
+ * PADDW rd, rs, rt Parallel Add Word
+ * PSUBW rd, rs, rt Parallel Subtract Word
+ * PADSBH rd, rs, rt Parallel Add/Subtract Halfword
+ * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte
+ * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte
+ * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword
+ * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword
+ * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word
+ * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word
+ * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte
+ * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte
+ * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword
+ * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword
+ * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word
+ * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word
+ */
+
+/*
+ * Min/Max (4 instructions)
+ * ------------------------
+ * PMAXH rd, rs, rt Parallel Maximum Halfword
+ * PMINH rd, rs, rt Parallel Minimum Halfword
+ * PMAXW rd, rs, rt Parallel Maximum Word
+ * PMINW rd, rs, rt Parallel Minimum Word
+ */
+
+/*
+ * Absolute (2 instructions)
+ * -------------------------
+ * PABSH rd, rt Parallel Absolute Halfword
+ * PABSW rd, rt Parallel Absolute Word
+ */
+
+/*
+ * Logical (4 instructions)
+ * ------------------------
+ * PAND rd, rs, rt Parallel AND
+ * POR rd, rs, rt Parallel OR
+ * PXOR rd, rs, rt Parallel XOR
+ * PNOR rd, rs, rt Parallel NOR
+ */
+
+/*
+ * Shift (9 instructions)
+ * ----------------------
+ * PSLLH rd, rt, sa Parallel Shift Left Logical Halfword
+ * PSRLH rd, rt, sa Parallel Shift Right Logical Halfword
+ * PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword
+ * PSLLW rd, rt, sa Parallel Shift Left Logical Word
+ * PSRLW rd, rt, sa Parallel Shift Right Logical Word
+ * PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word
+ * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word
+ * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word
+ * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word
+ */
+
+/*
+ * Compare (6 instructions)
+ * ------------------------
+ * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte
+ * PCEQB rd, rs, rt Parallel Compare for Equal Byte
+ * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword
+ * PCEQH rd, rs, rt Parallel Compare for Equal Halfword
+ * PCGTW rd, rs, rt Parallel Compare for Greater Than Word
+ * PCEQW rd, rs, rt Parallel Compare for Equal Word
+ */
+
+/*
+ * LZC (1 instruction)
+ * -------------------
+ * PLZCW rd, rs Parallel Leading Zero or One Count Word
+ */
+
+/*
+ * Quadword Load and Store (2 instructions)
+ * ----------------------------------------
+ * LQ rt, offset(base) Load Quadword
+ * SQ rt, offset(base) Store Quadword
+ */
+
+/*
+ * Multiply and Divide (19 instructions)
+ * -------------------------------------
+ * PMULTW rd, rs, rt Parallel Multiply Word
+ * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word
+ * PDIVW rs, rt Parallel Divide Word
+ * PDIVUW rs, rt Parallel Divide Unsigned Word
+ * PMADDW rd, rs, rt Parallel Multiply-Add Word
+ * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word
+ * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word
+ * PMULTH rd, rs, rt Parallel Multiply Halfword
+ * PMADDH rd, rs, rt Parallel Multiply-Add Halfword
+ * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword
+ * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword
+ * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword
+ * PDIVBW rs, rt Parallel Divide Broadcast Word
+ * PMFHI rd Parallel Move From HI Register
+ * PMFLO rd Parallel Move From LO Register
+ * PMTHI rs Parallel Move To HI Register
+ * PMTLO rs Parallel Move To LO Register
+ * PMFHL rd Parallel Move From HI/LO Register
+ * PMTHL rs Parallel Move To HI/LO Register
+ */
+
+/*
+ * Pack/Extend (11 instructions)
+ * -----------------------------
+ * PPAC5 rd, rt Parallel Pack to 5 bits
+ * PPACB rd, rs, rt Parallel Pack to Byte
+ * PPACH rd, rs, rt Parallel Pack to Halfword
+ * PPACW rd, rs, rt Parallel Pack to Word
+ * PEXT5 rd, rt Parallel Extend Upper from 5 bits
+ * PEXTUB rd, rs, rt Parallel Extend Upper from Byte
+ * PEXTLB rd, rs, rt Parallel Extend Lower from Byte
+ * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword
+ * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword
+ * PEXTUW rd, rs, rt Parallel Extend Upper from Word
+ * PEXTLW rd, rs, rt Parallel Extend Lower from Word
+ */
+
+/*
+ * Others (16 instructions)
+ * ------------------------
+ * PCPYH rd, rt Parallel Copy Halfword
+ * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword
+ * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword
+ * PREVH rd, rt Parallel Reverse Halfword
+ * PINTH rd, rs, rt Parallel Interleave Halfword
+ * PINTEH rd, rs, rt Parallel Interleave Even Halfword
+ * PEXEH rd, rt Parallel Exchange Even Halfword
+ * PEXCH rd, rt Parallel Exchange Center Halfword
+ * PEXEW rd, rt Parallel Exchange Even Word
+ * PEXCW rd, rt Parallel Exchange Center Word
+ * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable
+ * MFSA rd Move from Shift Amount Register
+ * MTSA rs Move to Shift Amount Register
+ * MTSAB rs, immediate Move Byte Count to Shift Amount Register
+ * MTSAH rs, immediate Move Halfword Count to Shift Amount Register
+ * PROT3W rd, rt Parallel Rotate 3 Words
+ */
+
/* Parallel Copy Halfword */
static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
{
--
2.26.2
next prev parent reply other threads:[~2021-02-14 18:26 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-14 17:58 [RFC PATCH 00/42] target/mips: Reintroduce the R5900 CPU (with more testing) Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 01/42] linux-user/mips64: Restore setup_frame() for o32 ABI Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 02/42] linux-user/mips64: Support o32 ABI syscalls Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 03/42] target/mips/translate: Make cpu_HI/LO registers public Philippe Mathieu-Daudé
2021-02-15 16:12 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 04/42] target/mips: Promote 128-bit multimedia registers as global ones Philippe Mathieu-Daudé
2021-02-15 16:14 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 05/42] target/mips: Rename 128-bit upper halve GPR registers Philippe Mathieu-Daudé
2021-02-15 16:15 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 06/42] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers Philippe Mathieu-Daudé
2021-02-15 16:15 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 07/42] target/mips/translate: Use GPR move functions in gen_HILO1_tx79() Philippe Mathieu-Daudé
2021-02-15 16:17 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 08/42] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Philippe Mathieu-Daudé
2021-02-15 16:21 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 09/42] target/mips/tx79: Move MTHI1 / MTLO1 " Philippe Mathieu-Daudé
2021-02-15 16:23 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 10/42] target/mips/translate: Simplify PCPYH using deposit_i64() Philippe Mathieu-Daudé
2021-02-15 16:24 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 11/42] target/mips/tx79: Move PCPYH opcode to decodetree Philippe Mathieu-Daudé
2021-02-15 16:26 ` Richard Henderson
2021-03-08 10:48 ` Philippe Mathieu-Daudé
2021-03-08 11:57 ` Philippe Mathieu-Daudé
2021-03-09 14:25 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 12/42] target/mips/tx79: Move PCPYLD / PCPYUD opcodes " Philippe Mathieu-Daudé
2021-02-15 16:28 ` Richard Henderson
2021-02-15 16:58 ` Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 13/42] target/mips: Remove 'C790 Multimedia Instructions' dead code Philippe Mathieu-Daudé
2021-02-15 16:32 ` Richard Henderson
2021-02-14 17:58 ` Philippe Mathieu-Daudé [this message]
2021-02-15 16:33 ` [RFC PATCH 14/42] target/mips/tx79: Salvage instructions description comment Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 15/42] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic) Philippe Mathieu-Daudé
2021-02-15 16:35 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 16/42] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract) Philippe Mathieu-Daudé
2021-02-15 16:38 ` Richard Henderson
2021-03-08 18:46 ` Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 17/42] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word) Philippe Mathieu-Daudé
2021-02-15 16:44 ` Richard Henderson
2021-03-08 18:40 ` Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 18/42] target/mips/tx79: Introduce PEXTU[BHW] opcodes (Parallel Extend Lower) Philippe Mathieu-Daudé
2021-02-15 18:28 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 19/42] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal) Philippe Mathieu-Daudé
2021-02-15 20:32 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 20/42] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than) Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 21/42] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word) Philippe Mathieu-Daudé
2021-02-15 20:38 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 22/42] target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword) Philippe Mathieu-Daudé
2021-02-15 20:41 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 23/42] target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even) Philippe Mathieu-Daudé
2021-02-15 20:45 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 24/42] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words) Philippe Mathieu-Daudé
2021-02-15 20:49 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 25/42] target/mips/tx79: Introduce LQ opcode (Load Quadword) Philippe Mathieu-Daudé
2021-02-15 20:51 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 26/42] target/mips/tx79: Introduce SQ opcode (Store Quadword) Philippe Mathieu-Daudé
2021-02-15 20:51 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 27/42] target/mips/translate: Make gen_rdhwr() public Philippe Mathieu-Daudé
2021-02-15 20:51 ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 28/42] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ() Philippe Mathieu-Daudé
2021-02-15 21:01 ` Richard Henderson
2021-02-16 7:05 ` Fredrik Noring
2021-02-16 12:21 ` Maciej W. Rozycki
2021-02-16 13:04 ` Fredrik Noring
2021-02-14 17:58 ` [RFC PATCH 29/42] linux-user/mips64: Support the n32 ABI for the R5900 Philippe Mathieu-Daudé
2021-02-15 21:02 ` Richard Henderson
2021-02-14 17:59 ` [RFC PATCH 30/42] target/mips: Reintroduce the R5900 CPU Philippe Mathieu-Daudé
2021-02-15 21:04 ` Richard Henderson
2021-02-14 17:59 ` [RFC PATCH 31/42] default-configs: Support o32 ABI with R5900 64-bit MIPS CPU Philippe Mathieu-Daudé
2021-02-15 21:05 ` Richard Henderson
2021-02-14 17:59 ` [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image Philippe Mathieu-Daudé
2021-02-15 11:59 ` Daniel P. Berrangé
2021-02-15 13:45 ` Fredrik Noring
2021-02-20 20:01 ` Philippe Mathieu-Daudé
2021-03-12 15:10 ` Philippe Mathieu-Daudé
2021-03-12 17:05 ` Maciej W. Rozycki
2021-03-12 17:46 ` Philippe Mathieu-Daudé
2021-03-12 20:04 ` Maciej W. Rozycki
2021-03-13 7:02 ` Fredrik Noring
2021-03-17 18:55 ` Philippe Mathieu-Daudé
2021-03-17 22:21 ` Maciej W. Rozycki
2021-03-12 18:24 ` Fredrik Noring
2021-03-12 20:05 ` Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 33/42] gitlab-ci: Pass optional EXTRA_FILES when building docker images Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 34/42] gitlab-ci: Build MIPS R5900 cross-toolchain (Gentoo based) Philippe Mathieu-Daudé
2021-02-15 11:42 ` Philippe Mathieu-Daudé
2021-02-15 11:58 ` Daniel P. Berrangé
2021-02-14 17:59 ` [RFC PATCH 35/42] tests/tcg: Add MIPS R5900 to arches filter Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 36/42] tests/tcg/mips: Test user mode DMULT for the R5900 Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 37/42] gitlab-ci: Add job to test the MIPS r5900o32el target Philippe Mathieu-Daudé
2021-02-15 5:31 ` Thomas Huth
2021-02-15 8:07 ` Philippe Mathieu-Daudé
2021-02-15 8:11 ` Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 38/42] tests/acceptance: Extract QemuBaseTest from Test Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 39/42] tests/acceptance: Make pick_default_qemu_bin() more generic Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 40/42] tests/acceptance: Introduce QemuUserTest base class Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 41/42] tests/acceptance: Test R5900 CPU with BusyBox from Sony PS2 Philippe Mathieu-Daudé
2021-02-15 14:28 ` Fredrik Noring
2021-02-15 14:46 ` Maciej W. Rozycki
2021-02-14 17:59 ` [RFC PATCH 42/42] gitlab-ci: Add job to run integration tests for the r5900o32el target Philippe Mathieu-Daudé
2021-02-14 18:08 ` [RFC PATCH 00/42] target/mips: Reintroduce the R5900 CPU (with more testing) Philippe Mathieu-Daudé
2021-02-15 9:24 ` Philippe Mathieu-Daudé
2021-02-21 14:04 ` Philippe Mathieu-Daudé
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