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From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Fredrik Noring <noring@nocrew.org>
Cc: "Thomas Huth" <thuth@redhat.com>,
	qemu-devel@nongnu.org,
	"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Laurent Vivier" <laurent@vivier.eu>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: Re: [RFC PATCH 28/42] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ()
Date: Tue, 16 Feb 2021 13:21:34 +0100 (CET)	[thread overview]
Message-ID: <alpine.DEB.2.21.2102161244430.1521@angie.orcam.me.uk> (raw)
In-Reply-To: <YCtu1czHMjeixsj+@sx9>

On Tue, 16 Feb 2021, Fredrik Noring wrote:

> > Not that it's odd (the final address is masked, remember), but that it a store
> > to an address in the zero page.
> 
> The address always resolves to 0xffffe83b (then masked) in 32-bit KSEG2,
> because rt is always $3 and rd is always $29 so -6085(zero), hence the
> last page (which is much better) rather than the first, as Maciej
> discovered:
> 
> https://patchwork.kernel.org/comment/23824173/
> 
> Other possible RDHWR encodings are no longer used, and can therefore be
> ignored and revert to SQ:
> 
> https://patchwork.kernel.org/comment/23842167/

 Or rather were never used in the general case (I can't rule out someone 
using that stuff for something, but I wouldn't call it supported; I used 
some of it internally while evaluating the speed of RDHWR emulation before 
the use of $3 or indeed RDHWR was settled in the TLS psABI, though the 
actual code that ultimately went into Linux was developed independently).

> > I would do this as
> > 
> > {
> >   RDHWR_user  011111 00000 ..... ..... 00000 111011   @rd_rt
> >   SQ          011111 ..... ..... ................     @ldst
> > }
> 
> Both rd and rt have fixed values, as mentioned.

 I would suggest actually supporting variable `rt', see below.  Would it 
be a problem?

> For reference, RDHWR is currently done like this in the Linux kernel:
> 
> 	if (IS_ENABLED(CONFIG_CPU_R5900)) {
> 		/*
> 		 * On the R5900, a valid RDHWR instruction
> 		 *
> 		 *     +--------+-------+----+----+-------+--------+
> 		 *     | 011111 | 00000 | rt | rd | 00000 | 111011 |
> 		 *     +--------+-------+----+----+-------+--------+
> 		 *          6       5      5    5     5        6
> 		 *
> 		 * having rt $3 (v1) and rd $29 (MIPS_HWR_ULR) is
> 		 * interpreted as the R5900 specific SQ instruction
> 		 *
> 		 *     +--------+-------+----+---------------------+
> 		 *     | 011111 |  base | rt |        offset       |
> 		 *     +--------+-------+----+---------------------+
> 		 *          6       5      5            16
> 		 *
> 		 * with
> 		 *
> 		 *     sq v1,-6085(zero)
> 		 *
> 		 * that asserts an address exception since -6085(zero)
> 		 * always resolves to 0xffffe83b in 32-bit KSEG2.
> 		 *
> 		 * Other legacy values of rd, such as MIPS_HWR_CPUNUM,
> 		 * are ignored.
> 		 */
> 		if (insn.r_format.func == rdhwr_op &&
> 		    insn.r_format.rd == MIPS_HWR_ULR &&
> 		    insn.r_format.rt == 3 &&

 I suggest leaving the `rt' check out for consistency, as changing the 
register to read the value of UserLocal into from psABI-mandated $3 does 
not cause any issue with the R5900 (the `rt' field overlaps between both 
machine instructions, so the encoding placed there does not affect the 
KSEG2 access trap caused) and those encodings are also emulated in the 
slow path for other legacy ISA CPUs:

	case MIPS_HWR_ULR:		/* Read UserLocal register */
		regs->regs[rt] = ti->tp_value;
		return 0;


 So e.g. `rdhwr $25, $29' is interpreted as `sq $25,-6085($0)' by the 
R5900 => no issue, it still traps.

 I know I have previously written that we can ignore `rt' encodings other 
than $3, but they are harmless and handling them saves a couple of machine 
instructions needed to make the check, so I think while we can, we do not 
actually have to ignore them.

> 		    insn.r_format.rs == 0 &&
> 		    insn.r_format.re == 0) {
> 			if (compute_return_epc(regs) < 0 ||
> 			    simulate_rdhwr(regs, insn.r_format.rd,
> 					   insn.r_format.rt) < 0)
> 				goto sigill;
> 			return;
> 		}
> 		goto sigbus;
> 	} else ...

 Code continuation quoted left for reference.

  Maciej


  reply	other threads:[~2021-02-16 12:22 UTC|newest]

Thread overview: 102+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-14 17:58 [RFC PATCH 00/42] target/mips: Reintroduce the R5900 CPU (with more testing) Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 01/42] linux-user/mips64: Restore setup_frame() for o32 ABI Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 02/42] linux-user/mips64: Support o32 ABI syscalls Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 03/42] target/mips/translate: Make cpu_HI/LO registers public Philippe Mathieu-Daudé
2021-02-15 16:12   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 04/42] target/mips: Promote 128-bit multimedia registers as global ones Philippe Mathieu-Daudé
2021-02-15 16:14   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 05/42] target/mips: Rename 128-bit upper halve GPR registers Philippe Mathieu-Daudé
2021-02-15 16:15   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 06/42] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers Philippe Mathieu-Daudé
2021-02-15 16:15   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 07/42] target/mips/translate: Use GPR move functions in gen_HILO1_tx79() Philippe Mathieu-Daudé
2021-02-15 16:17   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 08/42] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Philippe Mathieu-Daudé
2021-02-15 16:21   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 09/42] target/mips/tx79: Move MTHI1 / MTLO1 " Philippe Mathieu-Daudé
2021-02-15 16:23   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 10/42] target/mips/translate: Simplify PCPYH using deposit_i64() Philippe Mathieu-Daudé
2021-02-15 16:24   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 11/42] target/mips/tx79: Move PCPYH opcode to decodetree Philippe Mathieu-Daudé
2021-02-15 16:26   ` Richard Henderson
2021-03-08 10:48     ` Philippe Mathieu-Daudé
2021-03-08 11:57       ` Philippe Mathieu-Daudé
2021-03-09 14:25         ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 12/42] target/mips/tx79: Move PCPYLD / PCPYUD opcodes " Philippe Mathieu-Daudé
2021-02-15 16:28   ` Richard Henderson
2021-02-15 16:58     ` Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 13/42] target/mips: Remove 'C790 Multimedia Instructions' dead code Philippe Mathieu-Daudé
2021-02-15 16:32   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 14/42] target/mips/tx79: Salvage instructions description comment Philippe Mathieu-Daudé
2021-02-15 16:33   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 15/42] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic) Philippe Mathieu-Daudé
2021-02-15 16:35   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 16/42] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract) Philippe Mathieu-Daudé
2021-02-15 16:38   ` Richard Henderson
2021-03-08 18:46     ` Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 17/42] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word) Philippe Mathieu-Daudé
2021-02-15 16:44   ` Richard Henderson
2021-03-08 18:40     ` Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 18/42] target/mips/tx79: Introduce PEXTU[BHW] opcodes (Parallel Extend Lower) Philippe Mathieu-Daudé
2021-02-15 18:28   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 19/42] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal) Philippe Mathieu-Daudé
2021-02-15 20:32   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 20/42] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than) Philippe Mathieu-Daudé
2021-02-14 17:58 ` [RFC PATCH 21/42] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word) Philippe Mathieu-Daudé
2021-02-15 20:38   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 22/42] target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword) Philippe Mathieu-Daudé
2021-02-15 20:41   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 23/42] target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even) Philippe Mathieu-Daudé
2021-02-15 20:45   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 24/42] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words) Philippe Mathieu-Daudé
2021-02-15 20:49   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 25/42] target/mips/tx79: Introduce LQ opcode (Load Quadword) Philippe Mathieu-Daudé
2021-02-15 20:51   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 26/42] target/mips/tx79: Introduce SQ opcode (Store Quadword) Philippe Mathieu-Daudé
2021-02-15 20:51   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 27/42] target/mips/translate: Make gen_rdhwr() public Philippe Mathieu-Daudé
2021-02-15 20:51   ` Richard Henderson
2021-02-14 17:58 ` [RFC PATCH 28/42] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ() Philippe Mathieu-Daudé
2021-02-15 21:01   ` Richard Henderson
2021-02-16  7:05     ` Fredrik Noring
2021-02-16 12:21       ` Maciej W. Rozycki [this message]
2021-02-16 13:04         ` Fredrik Noring
2021-02-14 17:58 ` [RFC PATCH 29/42] linux-user/mips64: Support the n32 ABI for the R5900 Philippe Mathieu-Daudé
2021-02-15 21:02   ` Richard Henderson
2021-02-14 17:59 ` [RFC PATCH 30/42] target/mips: Reintroduce the R5900 CPU Philippe Mathieu-Daudé
2021-02-15 21:04   ` Richard Henderson
2021-02-14 17:59 ` [RFC PATCH 31/42] default-configs: Support o32 ABI with R5900 64-bit MIPS CPU Philippe Mathieu-Daudé
2021-02-15 21:05   ` Richard Henderson
2021-02-14 17:59 ` [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image Philippe Mathieu-Daudé
2021-02-15 11:59   ` Daniel P. Berrangé
2021-02-15 13:45     ` Fredrik Noring
2021-02-20 20:01       ` Philippe Mathieu-Daudé
2021-03-12 15:10         ` Philippe Mathieu-Daudé
2021-03-12 17:05           ` Maciej W. Rozycki
2021-03-12 17:46             ` Philippe Mathieu-Daudé
2021-03-12 20:04               ` Maciej W. Rozycki
2021-03-13  7:02                 ` Fredrik Noring
2021-03-17 18:55                 ` Philippe Mathieu-Daudé
2021-03-17 22:21                   ` Maciej W. Rozycki
2021-03-12 18:24             ` Fredrik Noring
2021-03-12 20:05               ` Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 33/42] gitlab-ci: Pass optional EXTRA_FILES when building docker images Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 34/42] gitlab-ci: Build MIPS R5900 cross-toolchain (Gentoo based) Philippe Mathieu-Daudé
2021-02-15 11:42   ` Philippe Mathieu-Daudé
2021-02-15 11:58     ` Daniel P. Berrangé
2021-02-14 17:59 ` [RFC PATCH 35/42] tests/tcg: Add MIPS R5900 to arches filter Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 36/42] tests/tcg/mips: Test user mode DMULT for the R5900 Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 37/42] gitlab-ci: Add job to test the MIPS r5900o32el target Philippe Mathieu-Daudé
2021-02-15  5:31   ` Thomas Huth
2021-02-15  8:07     ` Philippe Mathieu-Daudé
2021-02-15  8:11       ` Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 38/42] tests/acceptance: Extract QemuBaseTest from Test Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 39/42] tests/acceptance: Make pick_default_qemu_bin() more generic Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 40/42] tests/acceptance: Introduce QemuUserTest base class Philippe Mathieu-Daudé
2021-02-14 17:59 ` [RFC PATCH 41/42] tests/acceptance: Test R5900 CPU with BusyBox from Sony PS2 Philippe Mathieu-Daudé
2021-02-15 14:28   ` Fredrik Noring
2021-02-15 14:46     ` Maciej W. Rozycki
2021-02-14 17:59 ` [RFC PATCH 42/42] gitlab-ci: Add job to run integration tests for the r5900o32el target Philippe Mathieu-Daudé
2021-02-14 18:08 ` [RFC PATCH 00/42] target/mips: Reintroduce the R5900 CPU (with more testing) Philippe Mathieu-Daudé
2021-02-15  9:24 ` Philippe Mathieu-Daudé
2021-02-21 14:04 ` Philippe Mathieu-Daudé

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