From: Sergio Paracuellos <sergio.paracuellos@gmail.com> To: sboyd@kernel.org Cc: robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, neil@brown.name, linux-kernel@vger.kernel.org, Rob Herring <robh@kernel.org> Subject: [PATCH v11 2/6] dt: bindings: add mt7621-sysc device tree binding documentation Date: Tue, 9 Mar 2021 06:22:22 +0100 [thread overview] Message-ID: <20210309052226.29531-3-sergio.paracuellos@gmail.com> (raw) In-Reply-To: <20210309052226.29531-1-sergio.paracuellos@gmail.com> Adds device tree binding documentation for clocks in the MT7621 SOC. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml new file mode 100644 index 000000000000..915f84efd763 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 Clock Device Tree Bindings + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + The MT7621 has a PLL controller from where the cpu clock is provided + as well as derived clocks for the bus and the peripherals. It also + can gate SoC device clocks. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in: + [1]: <include/dt-bindings/clock/mt7621-clk.h>. + + The clocks are provided inside a system controller node. + +properties: + compatible: + items: + - const: mediatek,mt7621-sysc + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + + ralink,memctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of syscon used to control memory registers + + clock-output-names: + maxItems: 8 + +required: + - compatible + - reg + - '#clock-cells' + - ralink,memctl + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt7621-clk.h> + + sysc: sysc@0 { + compatible = "mediatek,mt7621-sysc", "syscon"; + reg = <0x0 0x100>; + #clock-cells = <1>; + ralink,memctl = <&memc>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; + }; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Sergio Paracuellos <sergio.paracuellos@gmail.com> To: sboyd@kernel.org Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org, tsbogend@alpha.franken.de, Rob Herring <robh@kernel.org>, gregkh@linuxfoundation.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, john@phrozen.org, neil@brown.name, linux-clk@vger.kernel.org Subject: [PATCH v11 2/6] dt: bindings: add mt7621-sysc device tree binding documentation Date: Tue, 9 Mar 2021 06:22:22 +0100 [thread overview] Message-ID: <20210309052226.29531-3-sergio.paracuellos@gmail.com> (raw) In-Reply-To: <20210309052226.29531-1-sergio.paracuellos@gmail.com> Adds device tree binding documentation for clocks in the MT7621 SOC. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml new file mode 100644 index 000000000000..915f84efd763 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 Clock Device Tree Bindings + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + The MT7621 has a PLL controller from where the cpu clock is provided + as well as derived clocks for the bus and the peripherals. It also + can gate SoC device clocks. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in: + [1]: <include/dt-bindings/clock/mt7621-clk.h>. + + The clocks are provided inside a system controller node. + +properties: + compatible: + items: + - const: mediatek,mt7621-sysc + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + + ralink,memctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of syscon used to control memory registers + + clock-output-names: + maxItems: 8 + +required: + - compatible + - reg + - '#clock-cells' + - ralink,memctl + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt7621-clk.h> + + sysc: sysc@0 { + compatible = "mediatek,mt7621-sysc", "syscon"; + reg = <0x0 0x100>; + #clock-cells = <1>; + ralink,memctl = <&memc>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; + }; -- 2.25.1 _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
next prev parent reply other threads:[~2021-03-09 5:23 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-09 5:22 [PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621 Sergio Paracuellos 2021-03-09 5:22 ` Sergio Paracuellos 2021-03-09 5:22 ` [PATCH v11 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks Sergio Paracuellos 2021-03-09 5:22 ` Sergio Paracuellos 2021-04-09 18:15 ` Stephen Boyd 2021-04-09 18:15 ` Stephen Boyd 2021-03-09 5:22 ` Sergio Paracuellos [this message] 2021-03-09 5:22 ` [PATCH v11 2/6] dt: bindings: add mt7621-sysc device tree binding documentation Sergio Paracuellos 2021-04-09 18:15 ` Stephen Boyd 2021-04-09 18:15 ` Stephen Boyd 2021-03-09 5:22 ` [PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC Sergio Paracuellos 2021-03-09 5:22 ` Sergio Paracuellos 2021-04-09 18:14 ` Stephen Boyd 2021-04-09 18:14 ` Stephen Boyd 2021-04-09 18:34 ` Sergio Paracuellos 2021-04-09 18:34 ` Sergio Paracuellos 2021-04-09 18:38 ` Stephen Boyd 2021-03-09 5:22 ` [PATCH v11 4/6] staging: mt7621-dts: make use of new 'mt7621-clk' Sergio Paracuellos 2021-03-09 5:22 ` Sergio Paracuellos 2021-03-09 5:22 ` [PATCH v11 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk' Sergio Paracuellos 2021-03-09 5:22 ` Sergio Paracuellos 2021-03-09 15:07 ` Thomas Bogendoerfer 2021-03-09 15:07 ` Thomas Bogendoerfer 2021-03-09 5:22 ` [PATCH v11 6/6] MAINTAINERS: add MT7621 CLOCK maintainer Sergio Paracuellos 2021-03-09 5:22 ` Sergio Paracuellos 2021-03-23 8:13 ` [PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621 Sergio Paracuellos 2021-03-23 8:13 ` Sergio Paracuellos 2021-04-09 18:17 ` Stephen Boyd 2021-04-09 18:25 ` Sergio Paracuellos 2021-04-09 18:31 ` Stephen Boyd
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