All of lore.kernel.org
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 04/39] dma: Introduce dma_aligned_pow2_mask()
Date: Fri, 12 Mar 2021 13:51:05 +0000	[thread overview]
Message-ID: <20210312135140.1099-5-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210312135140.1099-1-peter.maydell@linaro.org>

From: Eric Auger <eric.auger@redhat.com>

Currently get_naturally_aligned_size() is used by the intel iommu
to compute the maximum invalidation range based on @size which is
a power of 2 while being aligned with the @start address and less
than the maximum range defined by @gaw.

This helper is also useful for other iommu devices (virtio-iommu,
SMMUv3) to make sure IOMMU UNMAP notifiers only are called with
power of 2 range sizes.

Let's move this latter into dma-helpers.c and rename it into
dma_aligned_pow2_mask(). Also rewrite the helper so that it
accomodates UINT64_MAX values for the size mask and max mask.
It now returns a mask instead of a size. Change the caller.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-id: 20210309102742.30442-3-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/sysemu/dma.h  | 12 ++++++++++++
 hw/i386/intel_iommu.c | 30 +++++++-----------------------
 softmmu/dma-helpers.c | 26 ++++++++++++++++++++++++++
 3 files changed, 45 insertions(+), 23 deletions(-)

diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index a052f7bca3f..3201e7901db 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -296,4 +296,16 @@ uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg);
 void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
                     QEMUSGList *sg, enum BlockAcctType type);
 
+/**
+ * dma_aligned_pow2_mask: Return the address bit mask of the largest
+ * power of 2 size less or equal than @end - @start + 1, aligned with @start,
+ * and bounded by 1 << @max_addr_bits bits.
+ *
+ * @start: range start address
+ * @end: range end address (greater than @start)
+ * @max_addr_bits: max address bits (<= 64)
+ */
+uint64_t dma_aligned_pow2_mask(uint64_t start, uint64_t end,
+                               int max_addr_bits);
+
 #endif
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 3206f379f8b..6be8f329185 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -35,6 +35,7 @@
 #include "hw/i386/x86-iommu.h"
 #include "hw/pci-host/q35.h"
 #include "sysemu/kvm.h"
+#include "sysemu/dma.h"
 #include "sysemu/sysemu.h"
 #include "hw/i386/apic_internal.h"
 #include "kvm/kvm_i386.h"
@@ -3455,24 +3456,6 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
     return vtd_dev_as;
 }
 
-static uint64_t get_naturally_aligned_size(uint64_t start,
-                                           uint64_t size, int gaw)
-{
-    uint64_t max_mask = 1ULL << gaw;
-    uint64_t alignment = start ? start & -start : max_mask;
-
-    alignment = MIN(alignment, max_mask);
-    size = MIN(size, max_mask);
-
-    if (alignment <= size) {
-        /* Increase the alignment of start */
-        return alignment;
-    } else {
-        /* Find the largest page mask from size */
-        return 1ULL << (63 - clz64(size));
-    }
-}
-
 /* Unmap the whole range in the notifier's scope. */
 static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
 {
@@ -3501,13 +3484,14 @@ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
 
     while (remain >= VTD_PAGE_SIZE) {
         IOMMUTLBEvent event;
-        uint64_t mask = get_naturally_aligned_size(start, remain, s->aw_bits);
+        uint64_t mask = dma_aligned_pow2_mask(start, end, s->aw_bits);
+        uint64_t size = mask + 1;
 
-        assert(mask);
+        assert(size);
 
         event.type = IOMMU_NOTIFIER_UNMAP;
         event.entry.iova = start;
-        event.entry.addr_mask = mask - 1;
+        event.entry.addr_mask = mask;
         event.entry.target_as = &address_space_memory;
         event.entry.perm = IOMMU_NONE;
         /* This field is meaningless for unmap */
@@ -3515,8 +3499,8 @@ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
 
         memory_region_notify_iommu_one(n, &event);
 
-        start += mask;
-        remain -= mask;
+        start += size;
+        remain -= size;
     }
 
     assert(!remain);
diff --git a/softmmu/dma-helpers.c b/softmmu/dma-helpers.c
index 29001b54595..7d766a5e89a 100644
--- a/softmmu/dma-helpers.c
+++ b/softmmu/dma-helpers.c
@@ -330,3 +330,29 @@ void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
 {
     block_acct_start(blk_get_stats(blk), cookie, sg->size, type);
 }
+
+uint64_t dma_aligned_pow2_mask(uint64_t start, uint64_t end, int max_addr_bits)
+{
+    uint64_t max_mask = UINT64_MAX, addr_mask = end - start;
+    uint64_t alignment_mask, size_mask;
+
+    if (max_addr_bits != 64) {
+        max_mask = (1ULL << max_addr_bits) - 1;
+    }
+
+    alignment_mask = start ? (start & -start) - 1 : max_mask;
+    alignment_mask = MIN(alignment_mask, max_mask);
+    size_mask = MIN(addr_mask, max_mask);
+
+    if (alignment_mask <= size_mask) {
+        /* Increase the alignment of start */
+        return alignment_mask;
+    } else {
+        /* Find the largest page mask from size */
+        if (addr_mask == UINT64_MAX) {
+            return UINT64_MAX;
+        }
+        return (1ULL << (63 - clz64(addr_mask + 1))) - 1;
+    }
+}
+
-- 
2.20.1



  parent reply	other threads:[~2021-03-12 13:57 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-12 13:51 [PULL 00/39] target-arm queue Peter Maydell
2021-03-12 13:51 ` [PULL 01/39] hw/misc: versal: Add a model of the XRAM controller Peter Maydell
2021-03-12 13:51 ` [PULL 02/39] hw/arm: versal: Add support for the XRAMs Peter Maydell
2021-03-12 13:51 ` [PULL 03/39] intel_iommu: Fix mask may be uninitialized in vtd_context_device_invalidate Peter Maydell
2021-03-12 13:51 ` Peter Maydell [this message]
2021-03-12 13:51 ` [PULL 05/39] virtio-iommu: Handle non power of 2 range invalidations Peter Maydell
2021-03-12 13:51 ` [PULL 06/39] hw/arm/smmu-common: Fix smmu_iotlb_inv_iova when asid is not set Peter Maydell
2021-03-12 13:51 ` [PULL 07/39] hw/arm/smmuv3: Enforce invalidation on a power of two range Peter Maydell
2021-03-12 13:51 ` [PULL 08/39] hw/arm/smmuv3: Fix SMMU_CMD_CFGI_STE_RANGE handling Peter Maydell
2021-03-12 13:51 ` [PULL 09/39] hw/arm/smmuv3: Uniformize sid traces Peter Maydell
2021-03-12 13:51 ` [PULL 10/39] target/arm: Fix sve_uzp_p vs odd vector lengths Peter Maydell
2021-03-12 13:51 ` [PULL 11/39] target/arm: Fix sve_zip_p " Peter Maydell
2021-03-12 13:51 ` [PULL 12/39] target/arm: Fix sve_punpk_p " Peter Maydell
2021-03-12 13:51 ` [PULL 13/39] target/arm: Update find_last_active for PREDDESC Peter Maydell
2021-03-12 13:51 ` [PULL 14/39] target/arm: Update BRKA, BRKB, BRKN " Peter Maydell
2021-03-12 13:51 ` [PULL 15/39] target/arm: Update CNTP " Peter Maydell
2021-03-12 13:51 ` [PULL 16/39] target/arm: Update WHILE " Peter Maydell
2021-03-12 13:51 ` [PULL 17/39] target/arm: Update sve reduction vs simd_desc Peter Maydell
2021-03-12 13:51 ` [PULL 18/39] hw/net/allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value Peter Maydell
2021-03-12 13:51 ` [PULL 19/39] tests/acceptance/boot_linux_console: remove Armbian 19.11.3 bionic test for orangepi-pc machine Peter Maydell
2021-03-12 13:51 ` [PULL 20/39] tests/acceptance/boot_linux_console: change URL for test_arm_orangepi_bionic_20_08 Peter Maydell
2021-03-12 13:51 ` [PULL 21/39] tests/acceptance: update sunxi kernel from armbian to 5.10.16 Peter Maydell
2021-03-12 13:51 ` [PULL 22/39] tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests Peter Maydell
2021-03-12 13:51 ` [PULL 23/39] hw/timer/sse-timer: Propagate eventual error in sse_timer_realize() Peter Maydell
2021-03-12 13:51 ` [PULL 24/39] accel: kvm: Fix kvm_type invocation Peter Maydell
2021-03-12 13:51 ` [PULL 25/39] hw/arm/virt: KVM: The IPA lower bound is 32 Peter Maydell
2021-03-12 13:51 ` [PULL 26/39] hw/misc: Add GPIOs for duty in NPCM7xx PWM Peter Maydell
2021-03-12 13:51 ` [PULL 27/39] hw/misc: Add NPCM7XX MFT Module Peter Maydell
2021-03-12 13:51 ` [PULL 28/39] hw/arm: Add MFT device to NPCM7xx Soc Peter Maydell
2021-03-12 13:51 ` [PULL 29/39] hw/arm: Connect PWM fans in NPCM7XX boards Peter Maydell
2021-03-12 13:51 ` [PULL 30/39] tests/qtest: Test PWM fan RPM using MFT in PWM test Peter Maydell
2021-03-12 13:51 ` [PULL 31/39] hw/display/pl110: Remove dead code for non-32-bpp surfaces Peter Maydell
2021-03-12 13:51 ` [PULL 32/39] hw/display/pl110: Pull included-once parts of template header into pl110.c Peter Maydell
2021-03-12 13:51 ` [PULL 33/39] hw/display/pl110: Remove use of BITS from pl110_template.h Peter Maydell
2021-03-12 13:51 ` [PULL 34/39] hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces Peter Maydell
2021-03-12 13:51 ` [PULL 35/39] hw/display/pxa2xx_lcd: Remove dest_width state field Peter Maydell
2021-03-12 13:51 ` [PULL 36/39] hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h Peter Maydell
2021-03-12 13:51 ` [PULL 37/39] hw/display/pxa2xx: Apply brace-related coding style fixes to template header Peter Maydell
2021-03-12 13:51 ` [PULL 38/39] hw/display/pxa2xx: Apply whitespace-only " Peter Maydell
2021-03-12 13:51 ` [PULL 39/39] hw/display/pxa2xx: Inline " Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210312135140.1099-5-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.