From: Adrien Grassein <adrien.grassein@gmail.com> To: unlisted-recipients:; (no To-header on input) Cc: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, l.stach@pengutronix.de, Anson.Huang@nxp.com, krzk@kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, qiangqing.zhang@nxp.com, alice.guo@nxp.com, aford173@gmail.com, agx@sigxcpu.org, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Adrien Grassein <adrien.grassein@gmail.com> Subject: [PATCH v1 0/7] imx-gpcv2 improvements Date: Wed, 7 Apr 2021 23:21:15 +0200 [thread overview] Message-ID: <20210407212122.626137-1-adrien.grassein@gmail.com> (raw) Hi, This patch set aims is to add the support of the i.MX8 MM power domains on the mainline kernel. To achieve this, I do several patches - Check errors when reading or writing registers (concerns i.MX8M base implementation); - Fix power up/down sequence. Handshake was not checked and it was not called at the appropriate time (concerns i.MX8M base implementaions); - Allow domains without power sequence control like the HSIOMIX of the i.MX8MM. - Add some i.MX8MM domains (HSIO and OTGS); - Introduce quirks. For example, i.MX8MM OTG domains should not be powered off (seen n the source code of th i.MX ATF). Quirks are easily upgrable for other cases. - Finally I defined power domains into the imx8mm.dtb file. I know that this kind of patch is rejected by NXP ut the other way (callin ATF directly) was also rejected. I also know that NXP is concerned abou adding hundred lines of codes for each new SOC but it' the way it works on Linux. And the "added code" mainly consist of adding structures, defines and generic methods for regmap. If it's a real problem, maybe we can introduc a new "gpcv3" driver for i.MX8MM, i.MX8MN and i.MX8MP. Thanks, Adrien Grassein (7): soc: imx: gpcv2: check for errors when r/w registers soc: imx: gpcv2: Fix power up/down sequence soc: imx: gpcv2: allow domains without power sequence control dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM soc: imx: gpcv2: add quirks to domains arm64: dts: imx8mm: add power-domains .../bindings/power/fsl,imx-gpcv2.yaml | 7 +- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 ++ drivers/soc/imx/gpcv2.c | 336 ++++++++++++++---- include/dt-bindings/power/imx8mm-power.h | 21 ++ 4 files changed, 333 insertions(+), 66 deletions(-) create mode 100644 include/dt-bindings/power/imx8mm-power.h -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Adrien Grassein <adrien.grassein@gmail.com> Cc: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, l.stach@pengutronix.de, Anson.Huang@nxp.com, krzk@kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, qiangqing.zhang@nxp.com, alice.guo@nxp.com, aford173@gmail.com, agx@sigxcpu.org, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Adrien Grassein <adrien.grassein@gmail.com> Subject: [PATCH v1 0/7] imx-gpcv2 improvements Date: Wed, 7 Apr 2021 23:21:15 +0200 [thread overview] Message-ID: <20210407212122.626137-1-adrien.grassein@gmail.com> (raw) Hi, This patch set aims is to add the support of the i.MX8 MM power domains on the mainline kernel. To achieve this, I do several patches - Check errors when reading or writing registers (concerns i.MX8M base implementation); - Fix power up/down sequence. Handshake was not checked and it was not called at the appropriate time (concerns i.MX8M base implementaions); - Allow domains without power sequence control like the HSIOMIX of the i.MX8MM. - Add some i.MX8MM domains (HSIO and OTGS); - Introduce quirks. For example, i.MX8MM OTG domains should not be powered off (seen n the source code of th i.MX ATF). Quirks are easily upgrable for other cases. - Finally I defined power domains into the imx8mm.dtb file. I know that this kind of patch is rejected by NXP ut the other way (callin ATF directly) was also rejected. I also know that NXP is concerned abou adding hundred lines of codes for each new SOC but it' the way it works on Linux. And the "added code" mainly consist of adding structures, defines and generic methods for regmap. If it's a real problem, maybe we can introduc a new "gpcv3" driver for i.MX8MM, i.MX8MN and i.MX8MP. Thanks, Adrien Grassein (7): soc: imx: gpcv2: check for errors when r/w registers soc: imx: gpcv2: Fix power up/down sequence soc: imx: gpcv2: allow domains without power sequence control dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM soc: imx: gpcv2: add quirks to domains arm64: dts: imx8mm: add power-domains .../bindings/power/fsl,imx-gpcv2.yaml | 7 +- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 ++ drivers/soc/imx/gpcv2.c | 336 ++++++++++++++---- include/dt-bindings/power/imx8mm-power.h | 21 ++ 4 files changed, 333 insertions(+), 66 deletions(-) create mode 100644 include/dt-bindings/power/imx8mm-power.h -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2021-04-07 21:21 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-07 21:21 Adrien Grassein [this message] 2021-04-07 21:21 ` [PATCH v1 0/7] imx-gpcv2 improvements Adrien Grassein 2021-04-07 21:21 ` [PATCH v1 1/7] soc: imx: gpcv2: check for errors when r/w registers Adrien Grassein 2021-04-07 21:21 ` Adrien Grassein 2021-04-12 17:16 ` Andrey Smirnov 2021-04-12 17:16 ` Andrey Smirnov 2021-04-07 21:21 ` [PATCH v1 2/7] soc: imx: gpcv2: Fix power up/down sequence Adrien Grassein 2021-04-07 21:21 ` Adrien Grassein 2021-04-07 21:21 ` [PATCH v1 3/7] soc: imx: gpcv2: allow domains without power sequence control Adrien Grassein 2021-04-07 21:21 ` Adrien Grassein 2021-04-07 21:21 ` [PATCH v1 4/7] dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM Adrien Grassein 2021-04-07 21:21 ` [PATCH v1 4/7] dt-bindings: power: fsl, imx-gpcv2: " Adrien Grassein 2021-04-07 21:21 ` [PATCH v1 5/7] soc: imx: gpcv2: add HSIOMIX and USB domains " Adrien Grassein 2021-04-07 21:21 ` Adrien Grassein 2021-04-07 21:21 ` [PATCH v1 6/7] soc: imx: gpcv2: add quirks to domains Adrien Grassein 2021-04-07 21:21 ` Adrien Grassein 2021-04-07 21:21 ` [PATCH v1 7/7] arm64: dts: imx8mm: add power-domains Adrien Grassein 2021-04-07 21:21 ` Adrien Grassein 2021-04-07 22:13 ` [PATCH v1 0/7] imx-gpcv2 improvements Lucas Stach 2021-04-07 22:13 ` Lucas Stach 2021-04-07 23:03 ` Adam Ford 2021-04-07 23:03 ` Adam Ford 2021-04-08 1:27 ` Peng Fan (OSS) 2021-04-08 1:27 ` Peng Fan (OSS) 2021-04-09 13:36 ` Adam Ford 2021-04-09 13:36 ` Adam Ford
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