From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH v6 3/3] pinctrl: Add Xilinx ZynqMP pinctrl driver support
Date: Fri, 23 Apr 2021 00:39:02 +0800 [thread overview]
Message-ID: <202104230042.PrSzeu9i-lkp@intel.com> (raw)
In-Reply-To: <1619080202-31924-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com>
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Hi Sai,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on v5.12-rc8]
[cannot apply to pinctrl/devel xlnx/master next-20210422]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Sai-Krishna-Potthuri/Add-ZynqMP-pinctrl-driver/20210422-163320
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-c024-20210421 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/889ebb6671b9d7a3a09e5f58e5060b90bcf4fe6b
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Sai-Krishna-Potthuri/Add-ZynqMP-pinctrl-driver/20210422-163320
git checkout 889ebb6671b9d7a3a09e5f58e5060b90bcf4fe6b
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross W=1 ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/pinctrl/pinctrl-zynqmp.c: In function 'zynqmp_pinconf_cfg_set':
>> drivers/pinctrl/pinctrl-zynqmp.c:419:8: error: 'PIN_CONFIG_MODE_LOW_POWER' undeclared (first use in this function)
419 | case PIN_CONFIG_MODE_LOW_POWER:
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-zynqmp.c:419:8: note: each undeclared identifier is reported only once for each function it appears in
vim +/PIN_CONFIG_MODE_LOW_POWER +419 drivers/pinctrl/pinctrl-zynqmp.c
332
333 /**
334 * zynqmp_pinconf_cfg_set() - Set requested config for the pin
335 * @pctldev: Pincontrol device pointer.
336 * @pin: Pin number.
337 * @configs: Configuration to set.
338 * @num_configs: Number of configurations.
339 *
340 * Loop through all configurations and call firmware API
341 * to set requested configurations for the pin.
342 *
343 * Return: 0 on success else error code.
344 */
345 static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev,
346 unsigned int pin, unsigned long *configs,
347 unsigned int num_configs)
348 {
349 int i, ret;
350
351 if (pin >= zynqmp_desc.npins)
352 return -EOPNOTSUPP;
353
354 for (i = 0; i < num_configs; i++) {
355 unsigned int param = pinconf_to_config_param(configs[i]);
356 unsigned int arg = pinconf_to_config_argument(configs[i]);
357 unsigned int value;
358
359 switch (param) {
360 case PIN_CONFIG_SLEW_RATE:
361 param = PM_PINCTRL_CONFIG_SLEW_RATE;
362 ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
363 break;
364 case PIN_CONFIG_BIAS_PULL_UP:
365 param = PM_PINCTRL_CONFIG_PULL_CTRL;
366 arg = PM_PINCTRL_BIAS_PULL_UP;
367 ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
368 break;
369 case PIN_CONFIG_BIAS_PULL_DOWN:
370 param = PM_PINCTRL_CONFIG_PULL_CTRL;
371 arg = PM_PINCTRL_BIAS_PULL_DOWN;
372 ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
373 break;
374 case PIN_CONFIG_BIAS_DISABLE:
375 param = PM_PINCTRL_CONFIG_BIAS_STATUS;
376 arg = PM_PINCTRL_BIAS_DISABLE;
377 ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
378 break;
379 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
380 param = PM_PINCTRL_CONFIG_SCHMITT_CMOS;
381 ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
382 break;
383 case PIN_CONFIG_DRIVE_STRENGTH:
384 switch (arg) {
385 case DRIVE_STRENGTH_2MA:
386 value = PM_PINCTRL_DRIVE_STRENGTH_2MA;
387 break;
388 case DRIVE_STRENGTH_4MA:
389 value = PM_PINCTRL_DRIVE_STRENGTH_4MA;
390 break;
391 case DRIVE_STRENGTH_8MA:
392 value = PM_PINCTRL_DRIVE_STRENGTH_8MA;
393 break;
394 case DRIVE_STRENGTH_12MA:
395 value = PM_PINCTRL_DRIVE_STRENGTH_12MA;
396 break;
397 default:
398 /* Invalid drive strength */
399 dev_warn(pctldev->dev,
400 "Invalid drive strength for pin %d\n",
401 pin);
402 return -EINVAL;
403 }
404
405 param = PM_PINCTRL_CONFIG_DRIVE_STRENGTH;
406 ret = zynqmp_pm_pinctrl_set_config(pin, param, value);
407 break;
408 case PIN_CONFIG_POWER_SOURCE:
409 param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS;
410 ret = zynqmp_pm_pinctrl_get_config(pin, param, &value);
411
412 if (arg != value)
413 dev_warn(pctldev->dev,
414 "Invalid IO Standard requested for pin %d\n",
415 pin);
416
417 break;
418 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
> 419 case PIN_CONFIG_MODE_LOW_POWER:
420 /*
421 * These cases are mentioned in dts but configurable
422 * registers are unknown. So falling through to ignore
423 * boot time warnings as of now.
424 */
425 ret = 0;
426 break;
427 default:
428 dev_warn(pctldev->dev,
429 "unsupported configuration parameter '%u'\n",
430 param);
431 ret = -EOPNOTSUPP;
432 break;
433 }
434
435 param = pinconf_to_config_param(configs[i]);
436 arg = pinconf_to_config_argument(configs[i]);
437 if (ret)
438 dev_warn(pctldev->dev,
439 "failed to set: pin %u param %u value %u\n",
440 pin, param, arg);
441 }
442
443 return 0;
444 }
445
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
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next prev parent reply other threads:[~2021-04-22 16:39 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-22 8:29 [PATCH v6 0/3] Add ZynqMP pinctrl driver Sai Krishna Potthuri
2021-04-22 8:29 ` Sai Krishna Potthuri
2021-04-22 8:30 ` [PATCH v6 1/3] firmware: xilinx: Add pinctrl support Sai Krishna Potthuri
2021-04-22 8:30 ` Sai Krishna Potthuri
2021-04-22 8:30 ` [PATCH v6 2/3] dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver Sai Krishna Potthuri
2021-04-22 8:30 ` Sai Krishna Potthuri
2021-04-22 8:30 ` [PATCH v6 3/3] pinctrl: Add Xilinx ZynqMP pinctrl driver support Sai Krishna Potthuri
2021-04-22 8:30 ` Sai Krishna Potthuri
2021-04-22 16:39 ` kernel test robot [this message]
2021-04-23 15:53 ` Andy Shevchenko
2021-04-23 15:53 ` Andy Shevchenko
2021-04-26 13:20 ` Sai Krishna Potthuri
2021-04-26 13:20 ` Sai Krishna Potthuri
2021-04-26 14:04 ` Andy Shevchenko
2021-04-26 14:04 ` Andy Shevchenko
2021-04-27 7:23 ` Michal Simek
2021-04-27 7:23 ` Michal Simek
2021-04-27 7:31 ` Andy Shevchenko
2021-04-27 7:31 ` Andy Shevchenko
2021-04-27 7:38 ` Michal Simek
2021-04-27 7:38 ` Michal Simek
2021-04-27 8:39 ` Andy Shevchenko
2021-04-27 8:39 ` Andy Shevchenko
2021-04-27 9:59 ` Michal Simek
2021-04-27 9:59 ` Michal Simek
2021-04-27 14:04 ` Andy Shevchenko
2021-04-27 14:04 ` Andy Shevchenko
2021-04-28 5:33 ` Sai Krishna Potthuri
2021-04-28 5:33 ` Sai Krishna Potthuri
2021-05-11 12:38 ` Sai Krishna Potthuri
2021-05-11 12:38 ` Sai Krishna Potthuri
2021-06-17 6:37 ` Sai Krishna Potthuri
2021-06-17 6:37 ` Sai Krishna Potthuri
2021-06-17 7:18 ` Andy Shevchenko
2021-06-17 7:18 ` Andy Shevchenko
2021-06-17 7:31 ` Greg Kroah-Hartman
2021-06-17 7:31 ` Greg Kroah-Hartman
2021-04-22 9:13 ` [PATCH v6 0/3] Add ZynqMP pinctrl driver Linus Walleij
2021-04-22 9:13 ` Linus Walleij
2021-04-23 15:54 ` Andy Shevchenko
2021-04-23 15:54 ` Andy Shevchenko
2021-04-29 14:21 ` Linus Walleij
2021-04-29 14:21 ` Linus Walleij
2021-04-29 14:32 ` Sai Krishna Potthuri
2021-04-29 14:32 ` Sai Krishna Potthuri
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