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From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Mark Brown <broonie@kernel.org>,
	Cezary Rojewski <cezary.rojewski@intel.com>,
	linux-input@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org,
	alsa-devel@alsa-project.org
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>,
	Daniel Mack <daniel@zonque.org>,
	Haojian Zhuang <haojian.zhuang@gmail.com>,
	Robert Jarzmik <robert.jarzmik@free.fr>,
	Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>,
	Liam Girdwood <liam.r.girdwood@linux.intel.com>,
	Jie Yang <yang.jie@linux.intel.com>,
	Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>
Subject: [PATCH v1 06/14] spi: pxa2xx: Group Intel Quark specific definitions
Date: Fri, 23 Apr 2021 19:34:29 +0300	[thread overview]
Message-ID: <20210423163437.89306-6-andriy.shevchenko@linux.intel.com> (raw)
In-Reply-To: <20210423163437.89306-1-andriy.shevchenko@linux.intel.com>

DDS_RATE is Intel Quark specific definition. Move it to the rest
Intel Quark related.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 include/linux/spi/pxa2xx_ssp.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/linux/spi/pxa2xx_ssp.h b/include/linux/spi/pxa2xx_ssp.h
index 14b049840faf..1b6c1a0922bd 100644
--- a/include/linux/spi/pxa2xx_ssp.h
+++ b/include/linux/spi/pxa2xx_ssp.h
@@ -38,7 +38,6 @@ struct device_node;
 #define SSDR		(0x10)  /* SSP Data Write/Data Read Register */
 
 #define SSTO		(0x28)  /* SSP Time Out Register */
-#define DDS_RATE	(0x28)  /* SSP DDS Clock Rate Register (Intel Quark) */
 #define SSPSP		(0x2C)  /* SSP Programmable Serial Protocol */
 #define SSTSA		(0x30)  /* SSP Tx Timeslot Active */
 #define SSRSA		(0x34)  /* SSP Rx Timeslot Active */
@@ -105,6 +104,9 @@ struct device_node;
 #define CE4100_SSCR1_RFT	GENMASK(11, 10)	/* Receive FIFO Threshold (mask) */
 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10)	/* level [1..4] */
 
+/* Intel Quark X1000 */
+#define DDS_RATE		0x28		 /* SSP DDS Clock Rate Register */
+
 /* QUARK_X1000 SSCR0 bit definition */
 #define QUARK_X1000_SSCR0_DSS		GENMASK(4, 0)	/* Data Size Select (mask) */
 #define QUARK_X1000_SSCR0_DataSize(x)	((x) - 1)	/* Data Size Select [4..32] */
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Mark Brown <broonie@kernel.org>,
	Cezary Rojewski <cezary.rojewski@intel.com>,
	linux-input@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org,
	alsa-devel@alsa-project.org
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>,
	Jie Yang <yang.jie@linux.intel.com>,
	Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>,
	Haojian Zhuang <haojian.zhuang@gmail.com>,
	Liam Girdwood <liam.r.girdwood@linux.intel.com>,
	Takashi Iwai <tiwai@suse.com>,
	Robert Jarzmik <robert.jarzmik@free.fr>,
	Daniel Mack <daniel@zonque.org>
Subject: [PATCH v1 06/14] spi: pxa2xx: Group Intel Quark specific definitions
Date: Fri, 23 Apr 2021 19:34:29 +0300	[thread overview]
Message-ID: <20210423163437.89306-6-andriy.shevchenko@linux.intel.com> (raw)
In-Reply-To: <20210423163437.89306-1-andriy.shevchenko@linux.intel.com>

DDS_RATE is Intel Quark specific definition. Move it to the rest
Intel Quark related.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 include/linux/spi/pxa2xx_ssp.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/linux/spi/pxa2xx_ssp.h b/include/linux/spi/pxa2xx_ssp.h
index 14b049840faf..1b6c1a0922bd 100644
--- a/include/linux/spi/pxa2xx_ssp.h
+++ b/include/linux/spi/pxa2xx_ssp.h
@@ -38,7 +38,6 @@ struct device_node;
 #define SSDR		(0x10)  /* SSP Data Write/Data Read Register */
 
 #define SSTO		(0x28)  /* SSP Time Out Register */
-#define DDS_RATE	(0x28)  /* SSP DDS Clock Rate Register (Intel Quark) */
 #define SSPSP		(0x2C)  /* SSP Programmable Serial Protocol */
 #define SSTSA		(0x30)  /* SSP Tx Timeslot Active */
 #define SSRSA		(0x34)  /* SSP Rx Timeslot Active */
@@ -105,6 +104,9 @@ struct device_node;
 #define CE4100_SSCR1_RFT	GENMASK(11, 10)	/* Receive FIFO Threshold (mask) */
 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10)	/* level [1..4] */
 
+/* Intel Quark X1000 */
+#define DDS_RATE		0x28		 /* SSP DDS Clock Rate Register */
+
 /* QUARK_X1000 SSCR0 bit definition */
 #define QUARK_X1000_SSCR0_DSS		GENMASK(4, 0)	/* Data Size Select (mask) */
 #define QUARK_X1000_SSCR0_DataSize(x)	((x) - 1)	/* Data Size Select [4..32] */
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Mark Brown <broonie@kernel.org>,
	Cezary Rojewski <cezary.rojewski@intel.com>,
	linux-input@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org,
	alsa-devel@alsa-project.org
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>,
	Daniel Mack <daniel@zonque.org>,
	Haojian Zhuang <haojian.zhuang@gmail.com>,
	Robert Jarzmik <robert.jarzmik@free.fr>,
	Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>,
	Liam Girdwood <liam.r.girdwood@linux.intel.com>,
	Jie Yang <yang.jie@linux.intel.com>,
	Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>
Subject: [PATCH v1 06/14] spi: pxa2xx: Group Intel Quark specific definitions
Date: Fri, 23 Apr 2021 19:34:29 +0300	[thread overview]
Message-ID: <20210423163437.89306-6-andriy.shevchenko@linux.intel.com> (raw)
In-Reply-To: <20210423163437.89306-1-andriy.shevchenko@linux.intel.com>

DDS_RATE is Intel Quark specific definition. Move it to the rest
Intel Quark related.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 include/linux/spi/pxa2xx_ssp.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/linux/spi/pxa2xx_ssp.h b/include/linux/spi/pxa2xx_ssp.h
index 14b049840faf..1b6c1a0922bd 100644
--- a/include/linux/spi/pxa2xx_ssp.h
+++ b/include/linux/spi/pxa2xx_ssp.h
@@ -38,7 +38,6 @@ struct device_node;
 #define SSDR		(0x10)  /* SSP Data Write/Data Read Register */
 
 #define SSTO		(0x28)  /* SSP Time Out Register */
-#define DDS_RATE	(0x28)  /* SSP DDS Clock Rate Register (Intel Quark) */
 #define SSPSP		(0x2C)  /* SSP Programmable Serial Protocol */
 #define SSTSA		(0x30)  /* SSP Tx Timeslot Active */
 #define SSRSA		(0x34)  /* SSP Rx Timeslot Active */
@@ -105,6 +104,9 @@ struct device_node;
 #define CE4100_SSCR1_RFT	GENMASK(11, 10)	/* Receive FIFO Threshold (mask) */
 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10)	/* level [1..4] */
 
+/* Intel Quark X1000 */
+#define DDS_RATE		0x28		 /* SSP DDS Clock Rate Register */
+
 /* QUARK_X1000 SSCR0 bit definition */
 #define QUARK_X1000_SSCR0_DSS		GENMASK(4, 0)	/* Data Size Select (mask) */
 #define QUARK_X1000_SSCR0_DataSize(x)	((x) - 1)	/* Data Size Select [4..32] */
-- 
2.30.2


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  parent reply	other threads:[~2021-04-23 16:34 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-23 16:34 [PATCH v1 01/14] spi: pxa2xx: Use one point of return when ->probe() fails Andy Shevchenko
2021-04-23 16:34 ` Andy Shevchenko
2021-04-23 16:34 ` Andy Shevchenko
2021-04-23 16:34 ` [PATCH v1 02/14] spi: pxa2xx: Utilize MMIO and physical base from struct ssp_device Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34 ` [PATCH v1 03/14] spi: pxa2xx: Utilize struct device " Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34 ` [PATCH v1 04/14] spi: pxa2xx: Replace header inclusions by forward declarations Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34 ` [PATCH v1 05/14] spi: pxa2xx: Consolidate related headers under include/linux/spi Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:56   ` Mark Brown
2021-04-23 16:56     ` Mark Brown
2021-04-23 16:56     ` Mark Brown
2021-04-23 17:30     ` Andy Shevchenko
2021-04-23 17:30       ` Andy Shevchenko
2021-04-23 17:30       ` Andy Shevchenko
2021-04-23 17:49       ` Mark Brown
2021-04-23 17:49         ` Mark Brown
2021-04-23 17:49         ` Mark Brown
2021-04-23 16:34 ` Andy Shevchenko [this message]
2021-04-23 16:34   ` [PATCH v1 06/14] spi: pxa2xx: Group Intel Quark specific definitions Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34 ` [PATCH v1 07/14] spi: pxa2xx: Introduce int_stop_and_reset() helper Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34 ` [PATCH v1 08/14] spi: pxa2xx: Reuse int_error_stop() in pxa2xx_spi_slave_abort() Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34 ` [PATCH v1 09/14] spi: pxa2xx: Use pxa_ssp_enable()/pxa_ssp_disable() in the driver Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34 ` [PATCH v1 10/14] spi: pxa2xx: Extract pxa2xx_spi_update() helper Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34 ` [PATCH v1 11/14] spi: pxa2xx: Extract clear_SSCR1_bits() helper Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34 ` [PATCH v1 12/14] spi: pxa2xx: Extract read_SSSR_bits() helper Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34 ` [PATCH v1 13/14] spi: pxa2xx: Constify struct driver_data parameter Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34 ` [PATCH v1 14/14] spi: pxa2xx: Introduce special type for Merrifield SPIs Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko
2021-04-23 16:34   ` Andy Shevchenko

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