[PATCH 1/2] dt-bindings: arm: Document qcom,cpss-acc

From: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
To: Rob Herring <robh+dt@kernel.org>, Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Russell King <linux@armlinux.org.uk>,
	David Sterba <dsterba@suse.com>, Jens Axboe <axboe@kernel.dk>,
	Bartosz Dudziak <bartosz.dudziak@snejp.pl>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Kumar Gala <galak@codeaurora.org>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-msm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] dt-bindings: arm: Document qcom,cpss-acc
Date: Thu, 13 May 2021 17:34:41 +0200	[thread overview]
Message-ID: <20210513153442.52941-2-bartosz.dudziak@snejp.pl> (raw)
In-Reply-To: <20210513153442.52941-1-bartosz.dudziak@snejp.pl>

The CPSS ACC binding describes the clock, reset, and power domain
controller for a Cortex-A7 CPU.

Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
---
 .../devicetree/bindings/arm/cpus.yaml         |  7 ++--
 .../bindings/arm/msm/qcom,cpss-acc.yaml       | 41 +++++++++++++++++++
 2 files changed, 45 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml

diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 26b886b20b..f391e15184 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -204,6 +204,7 @@ properties:
           - marvell,mmp3-smp
           - mediatek,mt6589-smp
           - mediatek,mt81xx-tz-smp
+          - qcom,cpss-acc
           - qcom,gcc-msm8660
           - qcom,kpss-acc-v1
           - qcom,kpss-acc-v2
@@ -276,7 +277,7 @@ properties:
       Specifies the SAW* node associated with this CPU.
 
       Required for systems that have an "enable-method" property
-      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
+      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2" or "qcom,cpss-acc"
 
       * arm/msm/qcom,saw2.txt
 
@@ -286,9 +287,9 @@ properties:
       Specifies the ACC* node associated with this CPU.
 
       Required for systems that have an "enable-method" property
-      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
+      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2" or "qcom,cpss-acc"
 
-      * arm/msm/qcom,kpss-acc.txt
+      * arm/msm/qcom,kpss-acc.txt or arm/msm/qcom,cpss-acc.yaml
 
   rockchip,pmu:
     $ref: '/schemas/types.yaml#/definitions/phandle'
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml
new file mode 100644
index 0000000000..54efbc5e3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,cpss-acc.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/msm/qcom,cpss-acc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cortex-A7 Processor Sub-system (CPSS) Application Clock Controller (ACC)
+
+maintainers:
+  - Kumar Gala <galak@codeaurora.org>
+
+description: |
+  The CPSS ACC provides clock, power domain, and reset control to a Cortex-A7
+  processor. There is one ACC register region per CPU within the PSS remapped
+  region as well as an alias register region that remaps accesses to the ACC
+  associated with the CPU accessing the region.
+
+properties:
+  compatible:
+    enum:
+      - qcom,cpss-acc
+
+  reg:
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: ACC base register region
+      - description: optional ACC alias register region
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@f9088000 {
+      compatible = "qcom,cpss-acc";
+      reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
+    };
-- 
2.25.1

