From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 13/17] drm/i915/adl_p: Define and use ADL-P specific DP translation tables
Date: Tue, 18 May 2021 17:06:21 -0700 [thread overview]
Message-ID: <20210519000625.3184321-14-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20210519000625.3184321-1-lucas.demarchi@intel.com>
From: Mika Kahola <mika.kahola@intel.com>
Define and use DP voltage swing and pre-emphasis translation tables
for ADL-P.
v2:
- Update according to recent bspec updates; there are now separate
tables for RBR/HBR and HBR2/HBR3. (Anusha)
BSpec: 54956
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++-
.../drm/i915/display/intel_ddi_buf_trans.c | 53 +++++++++++++++++++
.../drm/i915/display/intel_ddi_buf_trans.h | 4 ++
3 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 38a4f251b9c9..e0adb14ecd0d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -985,6 +985,8 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
if (DISPLAY_VER(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
+ else if (IS_ALDERLAKE_P(dev_priv))
+ adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
else
tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
} else if (DISPLAY_VER(dev_priv) == 11) {
@@ -1431,7 +1433,10 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
return;
- ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
+ if (IS_ALDERLAKE_P(dev_priv))
+ ddi_translations = adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
+ else
+ ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
return;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 7bcdd5c12028..ce5d5d13b7c1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -735,6 +735,34 @@ static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
+static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans_hbr[] = {
+ /* VS pre-emp Non-trans mV Pre-emph dB */
+ { 0x7, 0x0, 0x01 }, /* 0 0 400mV 0 dB */
+ { 0x5, 0x0, 0x06 }, /* 0 1 400mV 3.5 dB */
+ { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */
+ { 0x0, 0x0, 0x17 }, /* 0 3 400mV 9.5 dB */
+ { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
+ { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */
+ { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
+ { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
+ { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
+ { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB */
+};
+
+static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3[] = {
+ /* VS pre-emp Non-trans mV Pre-emph dB */
+ { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
+ { 0x5, 0x0, 0x04 }, /* 0 1 400mV 3.5 dB */
+ { 0x2, 0x0, 0x0A }, /* 0 2 400mV 6 dB */
+ { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */
+ { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
+ { 0x2, 0x0, 0x06 }, /* 1 1 600mV 3.5 dB */
+ { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
+ { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
+ { 0x0, 0x0, 0x09 }, /* 2 1 800mV 3.5 dB */
+ { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB */
+};
+
bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
{
return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
@@ -1348,6 +1376,31 @@ tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
}
+static const struct tgl_dkl_phy_ddi_buf_trans *
+adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ if (crtc_state->port_clock > 270000) {
+ *n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3);
+ return adlp_dkl_phy_dp_ddi_trans_hbr;
+ }
+
+ *n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr);
+ return adlp_dkl_phy_dp_ddi_trans_hbr;
+}
+
+const struct tgl_dkl_phy_ddi_buf_trans *
+adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
+ else
+ return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *default_entry)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index f8f0ef87e977..4c2efab38642 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -67,6 +67,10 @@ bxt_get_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries);
+const struct tgl_dkl_phy_ddi_buf_trans *
+adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries);
const struct cnl_ddi_buf_trans *
tgl_get_combo_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
--
2.31.1
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next prev parent reply other threads:[~2021-05-19 0:07 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-19 0:06 [Intel-gfx] [CI 00/17] ADL-P: more reviewed patches Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 01/17] drm/i915/xelpd: Calculate VDSC RC parameters Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 02/17] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 03/17] drm/i915/adl_p: Add dedicated SAGV watermarks Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 04/17] drm/i915/adl_p: Setup ports/phys Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 05/17] drm/i915/adl_p: Implement TC sequences Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 06/17] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 07/17] drm/i915/adl_p: Add ddb allocation support Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 08/17] drm/i915: Introduce MBUS relative dbuf offsets Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 09/17] drm/i915/adl_p: MBUS programming Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 10/17] drm/i915/adl_p: Tx escape clock with DSI Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 11/17] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 12/17] drm/i915/display: Add PSR interrupt error check function Lucas De Marchi
2021-05-19 0:06 ` Lucas De Marchi [this message]
2021-05-19 0:06 ` [Intel-gfx] [CI 14/17] drm/i915/adl_p: Add PLL Support Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 15/17] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 16/17] drm/i915/adlp: Add PIPE_MISC2 programming Lucas De Marchi
2021-05-19 0:06 ` [Intel-gfx] [CI 17/17] drm/i915/adl_p: Update memory bandwidth parameters Lucas De Marchi
2021-05-19 0:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for ADL-P: more reviewed patches Patchwork
2021-05-19 0:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-19 0:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-20 6:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-05-20 6:57 ` Lucas De Marchi
2021-05-20 10:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for ADL-P: more reviewed patches (rev2) Patchwork
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