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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 04/17] drm/i915/adl_p: Setup ports/phys
Date: Tue, 18 May 2021 17:06:12 -0700	[thread overview]
Message-ID: <20210519000625.3184321-5-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20210519000625.3184321-1-lucas.demarchi@intel.com>

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

The SoC has 6 DDI ports(DDI A,DDI B and DDI TC1-4.
The first two are connected to combo phys while
the rest are connected to TC phys.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 47251b2bc8a4..953d363d9702 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3675,7 +3675,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	if (IS_TIGERLAKE(dev_priv))
+	if (IS_ALDERLAKE_P(dev_priv))
+		return phy >= PHY_F && phy <= PHY_I;
+	else if (IS_TIGERLAKE(dev_priv))
 		return phy >= PHY_D && phy <= PHY_I;
 	else if (IS_ICELAKE(dev_priv))
 		return phy >= PHY_C && phy <= PHY_F;
@@ -11251,7 +11253,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	if (IS_ALDERLAKE_S(dev_priv)) {
+	if (IS_ALDERLAKE_P(dev_priv)) {
+		intel_ddi_init(dev_priv, PORT_A);
+		intel_ddi_init(dev_priv, PORT_B);
+		intel_ddi_init(dev_priv, PORT_TC1);
+		intel_ddi_init(dev_priv, PORT_TC2);
+		intel_ddi_init(dev_priv, PORT_TC3);
+		intel_ddi_init(dev_priv, PORT_TC4);
+	} else if (IS_ALDERLAKE_S(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_TC1);
 		intel_ddi_init(dev_priv, PORT_TC2);
-- 
2.31.1

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  parent reply	other threads:[~2021-05-19  0:07 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-19  0:06 [Intel-gfx] [CI 00/17] ADL-P: more reviewed patches Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 01/17] drm/i915/xelpd: Calculate VDSC RC parameters Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 02/17] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 03/17] drm/i915/adl_p: Add dedicated SAGV watermarks Lucas De Marchi
2021-05-19  0:06 ` Lucas De Marchi [this message]
2021-05-19  0:06 ` [Intel-gfx] [CI 05/17] drm/i915/adl_p: Implement TC sequences Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 06/17] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 07/17] drm/i915/adl_p: Add ddb allocation support Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 08/17] drm/i915: Introduce MBUS relative dbuf offsets Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 09/17] drm/i915/adl_p: MBUS programming Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 10/17] drm/i915/adl_p: Tx escape clock with DSI Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 11/17] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 12/17] drm/i915/display: Add PSR interrupt error check function Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 13/17] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 14/17] drm/i915/adl_p: Add PLL Support Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 15/17] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 16/17] drm/i915/adlp: Add PIPE_MISC2 programming Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 17/17] drm/i915/adl_p: Update memory bandwidth parameters Lucas De Marchi
2021-05-19  0:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for ADL-P: more reviewed patches Patchwork
2021-05-19  0:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-19  0:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-20  6:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-05-20  6:57   ` Lucas De Marchi
2021-05-20 10:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for ADL-P: more reviewed patches (rev2) Patchwork

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