From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Paolo Bonzini <pbonzini@redhat.com>, Jonathan Corbet <corbet@lwn.net>, Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Alexander Graf <graf@amazon.com>, Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Damien Le Moal <damien.lemoal@wdc.com>, Anup Patel <anup@brainfault.org>, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Anup Patel <anup.patel@wdc.com> Subject: [PATCH v18 01/18] RISC-V: Add hypervisor extension related CSR defines Date: Wed, 19 May 2021 09:05:36 +0530 [thread overview] Message-ID: <20210519033553.1110536-2-anup.patel@wdc.com> (raw) In-Reply-To: <20210519033553.1110536-1-anup.patel@wdc.com> This patch adds asm/kvm_csr.h for RISC-V hypervisor extension related defines. Signed-off-by: Anup Patel <anup.patel@wdc.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alexander Graf <graf@amazon.com> --- arch/riscv/include/asm/kvm_csr.h | 105 +++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 arch/riscv/include/asm/kvm_csr.h diff --git a/arch/riscv/include/asm/kvm_csr.h b/arch/riscv/include/asm/kvm_csr.h new file mode 100644 index 000000000000..def91f53514c --- /dev/null +++ b/arch/riscv/include/asm/kvm_csr.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel <anup.patel@wdc.com> + */ + +#ifndef __RISCV_KVM_CSR_H__ +#define __RISCV_KVM_CSR_H__ + +#include <asm/csr.h> + +/* Interrupt causes (minus the high bit) */ +#define IRQ_VS_SOFT 2 +#define IRQ_VS_TIMER 6 +#define IRQ_VS_EXT 10 + + /* Exception causes */ +#define EXC_INST_ILLEGAL 2 +#define EXC_HYPERVISOR_SYSCALL 9 +#define EXC_SUPERVISOR_SYSCALL 10 +#define EXC_INST_GUEST_PAGE_FAULT 20 +#define EXC_LOAD_GUEST_PAGE_FAULT 21 +#define EXC_VIRTUAL_INST_FAULT 22 +#define EXC_STORE_GUEST_PAGE_FAULT 23 + +/* HSTATUS flags */ +#ifdef CONFIG_64BIT +#define HSTATUS_VSXL _AC(0x300000000, UL) +#define HSTATUS_VSXL_SHIFT 32 +#endif +#define HSTATUS_VTSR _AC(0x00400000, UL) +#define HSTATUS_VTW _AC(0x00200000, UL) +#define HSTATUS_VTVM _AC(0x00100000, UL) +#define HSTATUS_VGEIN _AC(0x0003f000, UL) +#define HSTATUS_VGEIN_SHIFT 12 +#define HSTATUS_HU _AC(0x00000200, UL) +#define HSTATUS_SPVP _AC(0x00000100, UL) +#define HSTATUS_SPV _AC(0x00000080, UL) +#define HSTATUS_GVA _AC(0x00000040, UL) +#define HSTATUS_VSBE _AC(0x00000020, UL) + +/* HGATP flags */ +#define HGATP_MODE_OFF _AC(0, UL) +#define HGATP_MODE_SV32X4 _AC(1, UL) +#define HGATP_MODE_SV39X4 _AC(8, UL) +#define HGATP_MODE_SV48X4 _AC(9, UL) + +#define HGATP32_MODE_SHIFT 31 +#define HGATP32_VMID_SHIFT 22 +#define HGATP32_VMID_MASK _AC(0x1FC00000, UL) +#define HGATP32_PPN _AC(0x003FFFFF, UL) + +#define HGATP64_MODE_SHIFT 60 +#define HGATP64_VMID_SHIFT 44 +#define HGATP64_VMID_MASK _AC(0x03FFF00000000000, UL) +#define HGATP64_PPN _AC(0x00000FFFFFFFFFFF, UL) + +#define HGATP_PAGE_SHIFT 12 + +#ifdef CONFIG_64BIT +#define HGATP_PPN HGATP64_PPN +#define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT +#define HGATP_VMID_MASK HGATP64_VMID_MASK +#define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT +#else +#define HGATP_PPN HGATP32_PPN +#define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT +#define HGATP_VMID_MASK HGATP32_VMID_MASK +#define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT +#endif + +/* VSIP & HVIP relation */ +#define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) +#define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ + (_AC(1, UL) << IRQ_S_TIMER) | \ + (_AC(1, UL) << IRQ_S_EXT)) + +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 + +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HIE 0x604 +#define CSR_HTIMEDELTA 0x605 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 +#define CSR_HTIMEDELTAH 0x615 +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HVIP 0x645 +#define CSR_HTINST 0x64a +#define CSR_HGATP 0x680 +#define CSR_HGEIP 0xe12 + +#endif -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Paolo Bonzini <pbonzini@redhat.com>, Jonathan Corbet <corbet@lwn.net>, Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Alexander Graf <graf@amazon.com>, Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Damien Le Moal <damien.lemoal@wdc.com>, Anup Patel <anup@brainfault.org>, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Anup Patel <anup.patel@wdc.com> Subject: [PATCH v18 01/18] RISC-V: Add hypervisor extension related CSR defines Date: Wed, 19 May 2021 09:05:36 +0530 [thread overview] Message-ID: <20210519033553.1110536-2-anup.patel@wdc.com> (raw) In-Reply-To: <20210519033553.1110536-1-anup.patel@wdc.com> This patch adds asm/kvm_csr.h for RISC-V hypervisor extension related defines. Signed-off-by: Anup Patel <anup.patel@wdc.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alexander Graf <graf@amazon.com> --- arch/riscv/include/asm/kvm_csr.h | 105 +++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 arch/riscv/include/asm/kvm_csr.h diff --git a/arch/riscv/include/asm/kvm_csr.h b/arch/riscv/include/asm/kvm_csr.h new file mode 100644 index 000000000000..def91f53514c --- /dev/null +++ b/arch/riscv/include/asm/kvm_csr.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel <anup.patel@wdc.com> + */ + +#ifndef __RISCV_KVM_CSR_H__ +#define __RISCV_KVM_CSR_H__ + +#include <asm/csr.h> + +/* Interrupt causes (minus the high bit) */ +#define IRQ_VS_SOFT 2 +#define IRQ_VS_TIMER 6 +#define IRQ_VS_EXT 10 + + /* Exception causes */ +#define EXC_INST_ILLEGAL 2 +#define EXC_HYPERVISOR_SYSCALL 9 +#define EXC_SUPERVISOR_SYSCALL 10 +#define EXC_INST_GUEST_PAGE_FAULT 20 +#define EXC_LOAD_GUEST_PAGE_FAULT 21 +#define EXC_VIRTUAL_INST_FAULT 22 +#define EXC_STORE_GUEST_PAGE_FAULT 23 + +/* HSTATUS flags */ +#ifdef CONFIG_64BIT +#define HSTATUS_VSXL _AC(0x300000000, UL) +#define HSTATUS_VSXL_SHIFT 32 +#endif +#define HSTATUS_VTSR _AC(0x00400000, UL) +#define HSTATUS_VTW _AC(0x00200000, UL) +#define HSTATUS_VTVM _AC(0x00100000, UL) +#define HSTATUS_VGEIN _AC(0x0003f000, UL) +#define HSTATUS_VGEIN_SHIFT 12 +#define HSTATUS_HU _AC(0x00000200, UL) +#define HSTATUS_SPVP _AC(0x00000100, UL) +#define HSTATUS_SPV _AC(0x00000080, UL) +#define HSTATUS_GVA _AC(0x00000040, UL) +#define HSTATUS_VSBE _AC(0x00000020, UL) + +/* HGATP flags */ +#define HGATP_MODE_OFF _AC(0, UL) +#define HGATP_MODE_SV32X4 _AC(1, UL) +#define HGATP_MODE_SV39X4 _AC(8, UL) +#define HGATP_MODE_SV48X4 _AC(9, UL) + +#define HGATP32_MODE_SHIFT 31 +#define HGATP32_VMID_SHIFT 22 +#define HGATP32_VMID_MASK _AC(0x1FC00000, UL) +#define HGATP32_PPN _AC(0x003FFFFF, UL) + +#define HGATP64_MODE_SHIFT 60 +#define HGATP64_VMID_SHIFT 44 +#define HGATP64_VMID_MASK _AC(0x03FFF00000000000, UL) +#define HGATP64_PPN _AC(0x00000FFFFFFFFFFF, UL) + +#define HGATP_PAGE_SHIFT 12 + +#ifdef CONFIG_64BIT +#define HGATP_PPN HGATP64_PPN +#define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT +#define HGATP_VMID_MASK HGATP64_VMID_MASK +#define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT +#else +#define HGATP_PPN HGATP32_PPN +#define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT +#define HGATP_VMID_MASK HGATP32_VMID_MASK +#define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT +#endif + +/* VSIP & HVIP relation */ +#define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) +#define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ + (_AC(1, UL) << IRQ_S_TIMER) | \ + (_AC(1, UL) << IRQ_S_EXT)) + +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 + +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HIE 0x604 +#define CSR_HTIMEDELTA 0x605 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 +#define CSR_HTIMEDELTAH 0x615 +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HVIP 0x645 +#define CSR_HTINST 0x64a +#define CSR_HGATP 0x680 +#define CSR_HGEIP 0xe12 + +#endif -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-05-19 3:37 UTC|newest] Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-19 3:35 [PATCH v18 00/18] KVM RISC-V Support Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` Anup Patel [this message] 2021-05-19 3:35 ` [PATCH v18 01/18] RISC-V: Add hypervisor extension related CSR defines Anup Patel 2021-05-19 3:35 ` [PATCH v18 02/18] RISC-V: Add initial skeletal KVM support Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 9:24 ` Dan Carpenter 2021-05-19 9:24 ` Dan Carpenter 2021-05-19 10:17 ` Dan Carpenter 2021-05-19 10:17 ` Dan Carpenter 2021-05-19 3:35 ` [PATCH v18 03/18] RISC-V: KVM: Implement VCPU create, init and destroy functions Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 04/18] RISC-V: KVM: Implement VCPU interrupts and requests handling Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 05/18] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 06/18] RISC-V: KVM: Implement VCPU world-switch Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 07/18] RISC-V: KVM: Handle MMIO exits for VCPU Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 08/18] RISC-V: KVM: Handle WFI " Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 09/18] RISC-V: KVM: Implement VMID allocator Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 10/18] RISC-V: KVM: Implement stage2 page table programming Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 11/18] RISC-V: KVM: Implement MMU notifiers Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 10:09 ` Dan Carpenter 2021-05-19 10:09 ` Dan Carpenter 2021-05-19 3:35 ` [PATCH v18 12/18] RISC-V: KVM: Add timer functionality Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 13/18] RISC-V: KVM: FP lazy save/restore Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 14/18] RISC-V: KVM: Implement ONE REG interface for FP registers Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 10:11 ` Dan Carpenter 2021-05-19 10:11 ` Dan Carpenter 2021-05-20 6:09 ` Dan Carpenter 2021-05-20 6:09 ` Dan Carpenter 2021-05-19 3:35 ` [PATCH v18 15/18] RISC-V: KVM: Add SBI v0.1 support Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 16/18] RISC-V: KVM: Document RISC-V specific parts of KVM API Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 17/18] RISC-V: KVM: Move sources to drivers/staging directory Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 3:35 ` [PATCH v18 18/18] RISC-V: KVM: Add MAINTAINERS entry Anup Patel 2021-05-19 3:35 ` Anup Patel 2021-05-19 4:58 ` [PATCH v18 00/18] KVM RISC-V Support Greg Kroah-Hartman 2021-05-19 4:58 ` Greg Kroah-Hartman 2021-05-19 5:10 ` Anup Patel 2021-05-19 5:10 ` Anup Patel 2021-05-19 5:10 ` Anup Patel 2021-05-19 5:21 ` Greg Kroah-Hartman 2021-05-19 5:21 ` Greg Kroah-Hartman 2021-05-19 10:47 ` Greg Kroah-Hartman 2021-05-19 10:47 ` Greg Kroah-Hartman 2021-05-19 11:18 ` Paolo Bonzini 2021-05-19 11:18 ` Paolo Bonzini 2021-05-19 12:23 ` Greg Kroah-Hartman 2021-05-19 12:23 ` Greg Kroah-Hartman 2021-05-19 13:29 ` Paolo Bonzini 2021-05-19 13:29 ` Paolo Bonzini 2021-05-19 13:58 ` Greg Kroah-Hartman 2021-05-19 13:58 ` Greg Kroah-Hartman 2021-05-19 15:08 ` Dan Carpenter 2021-05-19 15:08 ` Dan Carpenter 2021-05-19 15:26 ` Paolo Bonzini 2021-05-19 15:26 ` Paolo Bonzini 2021-05-21 17:13 ` Palmer Dabbelt 2021-05-21 17:13 ` Palmer Dabbelt 2021-05-21 17:21 ` Paolo Bonzini 2021-05-21 17:21 ` Paolo Bonzini 2021-05-21 17:47 ` Greg KH 2021-05-21 17:47 ` Greg KH 2021-05-21 18:08 ` Palmer Dabbelt 2021-05-21 18:08 ` Palmer Dabbelt 2021-05-21 18:25 ` Greg KH 2021-05-21 18:25 ` Greg KH 2021-05-21 20:25 ` Paolo Bonzini 2021-05-21 20:25 ` Paolo Bonzini 2021-05-24 7:09 ` Guo Ren 2021-05-24 7:09 ` Guo Ren 2021-05-24 7:09 ` Guo Ren 2021-05-24 22:57 ` Palmer Dabbelt 2021-05-24 22:57 ` Palmer Dabbelt 2021-05-24 23:08 ` Damien Le Moal 2021-05-24 23:08 ` Damien Le Moal 2021-05-25 7:37 ` Greg KH 2021-05-25 7:37 ` Greg KH 2021-05-25 8:01 ` Damien Le Moal 2021-05-25 8:01 ` Damien Le Moal 2021-05-25 8:11 ` Greg KH 2021-05-25 8:11 ` Greg KH 2021-05-25 8:24 ` Paolo Bonzini 2021-05-25 8:24 ` Paolo Bonzini
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