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From: Will Deacon <will@kernel.org>
To: Claire Chang <tientzu@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>,
	mpe@ellerman.id.au, Joerg Roedel <joro@8bytes.org>,
	Frank Rowand <frowand.list@gmail.com>,
	Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	boris.ostrovsky@oracle.com, jgross@suse.com,
	Christoph Hellwig <hch@lst.de>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	benh@kernel.crashing.org, paulus@samba.org,
	"list@263.net:IOMMU DRIVERS" <iommu@lists.linux-foundation.org>,
	sstabellini@kernel.org, Robin Murphy <robin.murphy@arm.com>,
	grant.likely@arm.com, xypron.glpk@gmx.de,
	Thierry Reding <treding@nvidia.com>,
	mingo@kernel.org, bauerman@linux.ibm.com, peterz@infradead.org,
	Greg KH <gregkh@linuxfoundation.org>,
	Saravana Kannan <saravanak@google.com>,
	"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
	heikki.krogerus@linux.intel.com,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	Dan Williams <dan.j.williams@intel.com>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>,
	linux-devicetree <devicetree@vger.kernel.org>,
	lkml <linux-kernel@vger.kernel.org>,
	linuxppc-dev@lists.ozlabs.org, xen-devel@lists.xenproject.org,
	Nicolas Boichat <drinkcat@chromium.org>,
	Jim Quinlan <james.quinlan@broadcom.com>,
	tfiga@chromium.org, bskeggs@redhat.com, bhelgaas@google.com,
	chris@chris-wilson.co.uk, daniel@ffwll.ch, airlied@linux.ie,
	dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	jani.nikula@linux.intel.com, jxgao@google.com,
	joonas.lahtinen@linux.intel.com, linux-pci@vger.kernel.org,
	maarten.lankhorst@linux.intel.com, matthew.auld@intel.com,
	rodrigo.vivi@intel.com, thomas.hellstrom@linux.intel.com
Subject: Re: [PATCH v7 14/15] dt-bindings: of: Add restricted DMA pool
Date: Wed, 26 May 2021 13:13:23 +0100	[thread overview]
Message-ID: <20210526121322.GA19313@willie-the-truck> (raw)
In-Reply-To: <20210518064215.2856977-15-tientzu@chromium.org>

Hi Claire,

On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> Introduce the new compatible string, restricted-dma-pool, for restricted
> DMA. One can specify the address and length of the restricted DMA memory
> region by restricted-dma-pool in the reserved-memory node.
> 
> Signed-off-by: Claire Chang <tientzu@chromium.org>
> ---
>  .../reserved-memory/reserved-memory.txt       | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> index e8d3096d922c..284aea659015 100644
> --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> +++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> @@ -51,6 +51,23 @@ compatible (optional) - standard definition
>            used as a shared pool of DMA buffers for a set of devices. It can
>            be used by an operating system to instantiate the necessary pool
>            management subsystem if necessary.
> +        - restricted-dma-pool: This indicates a region of memory meant to be
> +          used as a pool of restricted DMA buffers for a set of devices. The
> +          memory region would be the only region accessible to those devices.
> +          When using this, the no-map and reusable properties must not be set,
> +          so the operating system can create a virtual mapping that will be used
> +          for synchronization. The main purpose for restricted DMA is to
> +          mitigate the lack of DMA access control on systems without an IOMMU,
> +          which could result in the DMA accessing the system memory at
> +          unexpected times and/or unexpected addresses, possibly leading to data
> +          leakage or corruption. The feature on its own provides a basic level
> +          of protection against the DMA overwriting buffer contents at
> +          unexpected times. However, to protect against general data leakage and
> +          system memory corruption, the system needs to provide way to lock down
> +          the memory access, e.g., MPU. Note that since coherent allocation
> +          needs remapping, one must set up another device coherent pool by
> +          shared-dma-pool and use dma_alloc_from_dev_coherent instead for atomic
> +          coherent allocation.
>          - vendor specific string in the form <vendor>,[<device>-]<usage>
>  no-map (optional) - empty property
>      - Indicates the operating system must not create a virtual mapping
> @@ -120,6 +137,11 @@ one for multimedia processing (named multimedia-memory@77000000, 64MiB).
>  			compatible = "acme,multimedia-memory";
>  			reg = <0x77000000 0x4000000>;
>  		};
> +
> +		restricted_dma_mem_reserved: restricted_dma_mem_reserved {
> +			compatible = "restricted-dma-pool";
> +			reg = <0x50000000 0x400000>;
> +		};

nit: You need to update the old text that states "This example defines 3
contiguous regions ...".

>  	};
>  
>  	/* ... */
> @@ -138,4 +160,9 @@ one for multimedia processing (named multimedia-memory@77000000, 64MiB).
>  		memory-region = <&multimedia_reserved>;
>  		/* ... */
>  	};
> +
> +	pcie_device: pcie_device@0,0 {
> +		memory-region = <&restricted_dma_mem_reserved>;
> +		/* ... */
> +	};

I still don't understand how this works for individual PCIe devices -- how
is dev->of_node set to point at the node you have above?

I tried adding the memory-region to the host controller instead, and then
I see it crop up in dmesg:

  | pci-host-generic 40000000.pci: assigned reserved memory node restricted_dma_mem_reserved

but none of the actual PCI devices end up with 'dma_io_tlb_mem' set, and
so the restricted DMA area is not used. In fact, swiotlb isn't used at all.

What am I missing to make this work with PCIe devices?

Thanks,

Will

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Claire Chang <tientzu@chromium.org>
Cc: heikki.krogerus@linux.intel.com,
	thomas.hellstrom@linux.intel.com, peterz@infradead.org,
	joonas.lahtinen@linux.intel.com, dri-devel@lists.freedesktop.org,
	chris@chris-wilson.co.uk, grant.likely@arm.com, paulus@samba.org,
	Frank Rowand <frowand.list@gmail.com>,
	mingo@kernel.org, Marek Szyprowski <m.szyprowski@samsung.com>,
	sstabellini@kernel.org, Saravana Kannan <saravanak@google.com>,
	Joerg Roedel <joro@8bytes.org>,
	"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
	Christoph Hellwig <hch@lst.de>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>,
	bskeggs@redhat.com, linux-pci@vger.kernel.org,
	xen-devel@lists.xenproject.org,
	Thierry Reding <treding@nvidia.com>,
	intel-gfx@lists.freedesktop.org, matthew.auld@intel.com,
	linux-devicetree <devicetree@vger.kernel.org>,
	jxgao@google.com, daniel@ffwll.ch,
	Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	maarten.lankhorst@linux.intel.com, airlied@linux.ie,
	Dan Williams <dan.j.williams@intel.com>,
	linuxppc-dev@lists.ozlabs.org, jani.nikula@linux.intel.com,
	Rob Herring <robh+dt@kernel.org>,
	rodrigo.vivi@intel.com, bhelgaas@google.com,
	boris.ostrovsky@oracle.com,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	jgross@suse.com, Nicolas Boichat <drinkcat@chromium.org>,
	Greg KH <gregkh@linuxfoundation.org>,
	Randy Dunlap <rdunlap@infradead.org>,
	lkml <linux-kernel@vger.kernel.org>,
	tfiga@chromium.org,
	"list@263.net:IOMMU DRIVERS" <iommu@lists.linux-foundation.org>,
	Jim Quinlan <james.quinlan@broadcom.com>,
	xypron.glpk@gmx.de, Robin Murphy <robin.murphy@arm.com>,
	bauerman@linux.ibm.com
Subject: Re: [PATCH v7 14/15] dt-bindings: of: Add restricted DMA pool
Date: Wed, 26 May 2021 13:13:23 +0100	[thread overview]
Message-ID: <20210526121322.GA19313@willie-the-truck> (raw)
In-Reply-To: <20210518064215.2856977-15-tientzu@chromium.org>

Hi Claire,

On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> Introduce the new compatible string, restricted-dma-pool, for restricted
> DMA. One can specify the address and length of the restricted DMA memory
> region by restricted-dma-pool in the reserved-memory node.
> 
> Signed-off-by: Claire Chang <tientzu@chromium.org>
> ---
>  .../reserved-memory/reserved-memory.txt       | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> index e8d3096d922c..284aea659015 100644
> --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> +++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> @@ -51,6 +51,23 @@ compatible (optional) - standard definition
>            used as a shared pool of DMA buffers for a set of devices. It can
>            be used by an operating system to instantiate the necessary pool
>            management subsystem if necessary.
> +        - restricted-dma-pool: This indicates a region of memory meant to be
> +          used as a pool of restricted DMA buffers for a set of devices. The
> +          memory region would be the only region accessible to those devices.
> +          When using this, the no-map and reusable properties must not be set,
> +          so the operating system can create a virtual mapping that will be used
> +          for synchronization. The main purpose for restricted DMA is to
> +          mitigate the lack of DMA access control on systems without an IOMMU,
> +          which could result in the DMA accessing the system memory at
> +          unexpected times and/or unexpected addresses, possibly leading to data
> +          leakage or corruption. The feature on its own provides a basic level
> +          of protection against the DMA overwriting buffer contents at
> +          unexpected times. However, to protect against general data leakage and
> +          system memory corruption, the system needs to provide way to lock down
> +          the memory access, e.g., MPU. Note that since coherent allocation
> +          needs remapping, one must set up another device coherent pool by
> +          shared-dma-pool and use dma_alloc_from_dev_coherent instead for atomic
> +          coherent allocation.
>          - vendor specific string in the form <vendor>,[<device>-]<usage>
>  no-map (optional) - empty property
>      - Indicates the operating system must not create a virtual mapping
> @@ -120,6 +137,11 @@ one for multimedia processing (named multimedia-memory@77000000, 64MiB).
>  			compatible = "acme,multimedia-memory";
>  			reg = <0x77000000 0x4000000>;
>  		};
> +
> +		restricted_dma_mem_reserved: restricted_dma_mem_reserved {
> +			compatible = "restricted-dma-pool";
> +			reg = <0x50000000 0x400000>;
> +		};

nit: You need to update the old text that states "This example defines 3
contiguous regions ...".

>  	};
>  
>  	/* ... */
> @@ -138,4 +160,9 @@ one for multimedia processing (named multimedia-memory@77000000, 64MiB).
>  		memory-region = <&multimedia_reserved>;
>  		/* ... */
>  	};
> +
> +	pcie_device: pcie_device@0,0 {
> +		memory-region = <&restricted_dma_mem_reserved>;
> +		/* ... */
> +	};

I still don't understand how this works for individual PCIe devices -- how
is dev->of_node set to point at the node you have above?

I tried adding the memory-region to the host controller instead, and then
I see it crop up in dmesg:

  | pci-host-generic 40000000.pci: assigned reserved memory node restricted_dma_mem_reserved

but none of the actual PCI devices end up with 'dma_io_tlb_mem' set, and
so the restricted DMA area is not used. In fact, swiotlb isn't used at all.

What am I missing to make this work with PCIe devices?

Thanks,

Will

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Claire Chang <tientzu@chromium.org>
Cc: heikki.krogerus@linux.intel.com,
	thomas.hellstrom@linux.intel.com, peterz@infradead.org,
	benh@kernel.crashing.org, joonas.lahtinen@linux.intel.com,
	dri-devel@lists.freedesktop.org, chris@chris-wilson.co.uk,
	grant.likely@arm.com, paulus@samba.org,
	Frank Rowand <frowand.list@gmail.com>,
	mingo@kernel.org, sstabellini@kernel.org,
	Saravana Kannan <saravanak@google.com>,
	mpe@ellerman.id.au,
	"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
	Christoph Hellwig <hch@lst.de>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>,
	bskeggs@redhat.com, linux-pci@vger.kernel.org,
	xen-devel@lists.xenproject.org,
	Thierry Reding <treding@nvidia.com>,
	intel-gfx@lists.freedesktop.org, matthew.auld@intel.com,
	linux-devicetree <devicetree@vger.kernel.org>,
	jxgao@google.com, daniel@ffwll.ch,
	Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	maarten.lankhorst@linux.intel.com, airlied@linux.ie,
	Dan Williams <dan.j.williams@intel.com>,
	linuxppc-dev@lists.ozlabs.org, jani.nikula@linux.intel.com,
	Rob Herring <robh+dt@kernel.org>,
	rodrigo.vivi@intel.com, bhelgaas@google.com,
	boris.ostrovsky@oracle.com,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	jgross@suse.com, Nicolas Boichat <drinkcat@chromium.org>,
	Greg KH <gregkh@linuxfoundation.org>,
	Randy Dunlap <rdunlap@infradead.org>,
	lkml <linux-kernel@vger.kernel.org>,
	"list@263.net:IOMMU DRIVERS" <iommu@lists.linux-foundation.org>,
	Jim Quinlan <james.quinlan@broadcom.com>,
	xypron.glpk@gmx.de, Robin Murphy <robin.murphy@arm.com>,
	bauerman@linux.ibm.com
Subject: Re: [PATCH v7 14/15] dt-bindings: of: Add restricted DMA pool
Date: Wed, 26 May 2021 13:13:23 +0100	[thread overview]
Message-ID: <20210526121322.GA19313@willie-the-truck> (raw)
In-Reply-To: <20210518064215.2856977-15-tientzu@chromium.org>

Hi Claire,

On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> Introduce the new compatible string, restricted-dma-pool, for restricted
> DMA. One can specify the address and length of the restricted DMA memory
> region by restricted-dma-pool in the reserved-memory node.
> 
> Signed-off-by: Claire Chang <tientzu@chromium.org>
> ---
>  .../reserved-memory/reserved-memory.txt       | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> index e8d3096d922c..284aea659015 100644
> --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> +++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> @@ -51,6 +51,23 @@ compatible (optional) - standard definition
>            used as a shared pool of DMA buffers for a set of devices. It can
>            be used by an operating system to instantiate the necessary pool
>            management subsystem if necessary.
> +        - restricted-dma-pool: This indicates a region of memory meant to be
> +          used as a pool of restricted DMA buffers for a set of devices. The
> +          memory region would be the only region accessible to those devices.
> +          When using this, the no-map and reusable properties must not be set,
> +          so the operating system can create a virtual mapping that will be used
> +          for synchronization. The main purpose for restricted DMA is to
> +          mitigate the lack of DMA access control on systems without an IOMMU,
> +          which could result in the DMA accessing the system memory at
> +          unexpected times and/or unexpected addresses, possibly leading to data
> +          leakage or corruption. The feature on its own provides a basic level
> +          of protection against the DMA overwriting buffer contents at
> +          unexpected times. However, to protect against general data leakage and
> +          system memory corruption, the system needs to provide way to lock down
> +          the memory access, e.g., MPU. Note that since coherent allocation
> +          needs remapping, one must set up another device coherent pool by
> +          shared-dma-pool and use dma_alloc_from_dev_coherent instead for atomic
> +          coherent allocation.
>          - vendor specific string in the form <vendor>,[<device>-]<usage>
>  no-map (optional) - empty property
>      - Indicates the operating system must not create a virtual mapping
> @@ -120,6 +137,11 @@ one for multimedia processing (named multimedia-memory@77000000, 64MiB).
>  			compatible = "acme,multimedia-memory";
>  			reg = <0x77000000 0x4000000>;
>  		};
> +
> +		restricted_dma_mem_reserved: restricted_dma_mem_reserved {
> +			compatible = "restricted-dma-pool";
> +			reg = <0x50000000 0x400000>;
> +		};

nit: You need to update the old text that states "This example defines 3
contiguous regions ...".

>  	};
>  
>  	/* ... */
> @@ -138,4 +160,9 @@ one for multimedia processing (named multimedia-memory@77000000, 64MiB).
>  		memory-region = <&multimedia_reserved>;
>  		/* ... */
>  	};
> +
> +	pcie_device: pcie_device@0,0 {
> +		memory-region = <&restricted_dma_mem_reserved>;
> +		/* ... */
> +	};

I still don't understand how this works for individual PCIe devices -- how
is dev->of_node set to point at the node you have above?

I tried adding the memory-region to the host controller instead, and then
I see it crop up in dmesg:

  | pci-host-generic 40000000.pci: assigned reserved memory node restricted_dma_mem_reserved

but none of the actual PCI devices end up with 'dma_io_tlb_mem' set, and
so the restricted DMA area is not used. In fact, swiotlb isn't used at all.

What am I missing to make this work with PCIe devices?

Thanks,

Will
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Claire Chang <tientzu@chromium.org>
Cc: heikki.krogerus@linux.intel.com,
	thomas.hellstrom@linux.intel.com, peterz@infradead.org,
	dri-devel@lists.freedesktop.org, chris@chris-wilson.co.uk,
	grant.likely@arm.com, paulus@samba.org,
	Frank Rowand <frowand.list@gmail.com>,
	mingo@kernel.org, Marek Szyprowski <m.szyprowski@samsung.com>,
	sstabellini@kernel.org, Saravana Kannan <saravanak@google.com>,
	mpe@ellerman.id.au, Joerg Roedel <joro@8bytes.org>,
	"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
	Christoph Hellwig <hch@lst.de>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>,
	bskeggs@redhat.com, linux-pci@vger.kernel.org,
	xen-devel@lists.xenproject.org,
	Thierry Reding <treding@nvidia.com>,
	intel-gfx@lists.freedesktop.org, matthew.auld@intel.com,
	linux-devicetree <devicetree@vger.kernel.org>,
	jxgao@google.com, Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	airlied@linux.ie, Dan Williams <dan.j.williams@intel.com>,
	linuxppc-dev@lists.ozlabs.org, Rob Herring <robh+dt@kernel.org>,
	rodrigo.vivi@intel.com, bhelgaas@google.com,
	boris.ostrovsky@oracle.com,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	jgross@suse.com, Nicolas Boichat <drinkcat@chromium.org>,
	Greg KH <gregkh@linuxfoundation.org>,
	Randy Dunlap <rdunlap@infradead.org>,
	lkml <linux-kernel@vger.kernel.org>,
	tfiga@chromium.org,
	"list@263.net:IOMMU DRIVERS" <iommu@lists.linux-foundation.org>,
	Jim Quinlan <james.quinlan@broadcom.com>,
	xypron.glpk@gmx.de, Robin Murphy <robin.murphy@arm.com>,
	bauerman@linux.ibm.com
Subject: Re: [PATCH v7 14/15] dt-bindings: of: Add restricted DMA pool
Date: Wed, 26 May 2021 13:13:23 +0100	[thread overview]
Message-ID: <20210526121322.GA19313@willie-the-truck> (raw)
In-Reply-To: <20210518064215.2856977-15-tientzu@chromium.org>

Hi Claire,

On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> Introduce the new compatible string, restricted-dma-pool, for restricted
> DMA. One can specify the address and length of the restricted DMA memory
> region by restricted-dma-pool in the reserved-memory node.
> 
> Signed-off-by: Claire Chang <tientzu@chromium.org>
> ---
>  .../reserved-memory/reserved-memory.txt       | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> index e8d3096d922c..284aea659015 100644
> --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> +++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> @@ -51,6 +51,23 @@ compatible (optional) - standard definition
>            used as a shared pool of DMA buffers for a set of devices. It can
>            be used by an operating system to instantiate the necessary pool
>            management subsystem if necessary.
> +        - restricted-dma-pool: This indicates a region of memory meant to be
> +          used as a pool of restricted DMA buffers for a set of devices. The
> +          memory region would be the only region accessible to those devices.
> +          When using this, the no-map and reusable properties must not be set,
> +          so the operating system can create a virtual mapping that will be used
> +          for synchronization. The main purpose for restricted DMA is to
> +          mitigate the lack of DMA access control on systems without an IOMMU,
> +          which could result in the DMA accessing the system memory at
> +          unexpected times and/or unexpected addresses, possibly leading to data
> +          leakage or corruption. The feature on its own provides a basic level
> +          of protection against the DMA overwriting buffer contents at
> +          unexpected times. However, to protect against general data leakage and
> +          system memory corruption, the system needs to provide way to lock down
> +          the memory access, e.g., MPU. Note that since coherent allocation
> +          needs remapping, one must set up another device coherent pool by
> +          shared-dma-pool and use dma_alloc_from_dev_coherent instead for atomic
> +          coherent allocation.
>          - vendor specific string in the form <vendor>,[<device>-]<usage>
>  no-map (optional) - empty property
>      - Indicates the operating system must not create a virtual mapping
> @@ -120,6 +137,11 @@ one for multimedia processing (named multimedia-memory@77000000, 64MiB).
>  			compatible = "acme,multimedia-memory";
>  			reg = <0x77000000 0x4000000>;
>  		};
> +
> +		restricted_dma_mem_reserved: restricted_dma_mem_reserved {
> +			compatible = "restricted-dma-pool";
> +			reg = <0x50000000 0x400000>;
> +		};

nit: You need to update the old text that states "This example defines 3
contiguous regions ...".

>  	};
>  
>  	/* ... */
> @@ -138,4 +160,9 @@ one for multimedia processing (named multimedia-memory@77000000, 64MiB).
>  		memory-region = <&multimedia_reserved>;
>  		/* ... */
>  	};
> +
> +	pcie_device: pcie_device@0,0 {
> +		memory-region = <&restricted_dma_mem_reserved>;
> +		/* ... */
> +	};

I still don't understand how this works for individual PCIe devices -- how
is dev->of_node set to point at the node you have above?

I tried adding the memory-region to the host controller instead, and then
I see it crop up in dmesg:

  | pci-host-generic 40000000.pci: assigned reserved memory node restricted_dma_mem_reserved

but none of the actual PCI devices end up with 'dma_io_tlb_mem' set, and
so the restricted DMA area is not used. In fact, swiotlb isn't used at all.

What am I missing to make this work with PCIe devices?

Thanks,

Will

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Claire Chang <tientzu@chromium.org>
Cc: heikki.krogerus@linux.intel.com,
	thomas.hellstrom@linux.intel.com, peterz@infradead.org,
	benh@kernel.crashing.org, dri-devel@lists.freedesktop.org,
	chris@chris-wilson.co.uk, grant.likely@arm.com, paulus@samba.org,
	Frank Rowand <frowand.list@gmail.com>,
	mingo@kernel.org, Marek Szyprowski <m.szyprowski@samsung.com>,
	sstabellini@kernel.org, Saravana Kannan <saravanak@google.com>,
	mpe@ellerman.id.au, Joerg Roedel <joro@8bytes.org>,
	"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
	Christoph Hellwig <hch@lst.de>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>,
	bskeggs@redhat.com, linux-pci@vger.kernel.org,
	xen-devel@lists.xenproject.org,
	Thierry Reding <treding@nvidia.com>,
	intel-gfx@lists.freedesktop.org, matthew.auld@intel.com,
	linux-devicetree <devicetree@vger.kernel.org>,
	jxgao@google.com, Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	airlied@linux.ie, Dan Williams <dan.j.williams@intel.com>,
	linuxppc-dev@lists.ozlabs.org, Rob Herring <robh+dt@kernel.org>,
	bhelgaas@google.com, boris.ostrovsky@oracle.com,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	jgross@suse.com, Nicolas Boichat <drinkcat@chromium.org>,
	Greg KH <gregkh@linuxfoundation.org>,
	Randy Dunlap <rdunlap@infradead.org>,
	lkml <linux-kernel@vger.kernel.org>,
	tfiga@chromium.org,
	"list@263.net:IOMMU DRIVERS" <iommu@lists.linux-foundation.org>,
	Jim Quinlan <james.quinlan@broadcom.com>,
	xypron.glpk@gmx.de, Robin Murphy <robin.murphy@arm.com>,
	bauerman@linux.ibm.com
Subject: Re: [Intel-gfx] [PATCH v7 14/15] dt-bindings: of: Add restricted DMA pool
Date: Wed, 26 May 2021 13:13:23 +0100	[thread overview]
Message-ID: <20210526121322.GA19313@willie-the-truck> (raw)
In-Reply-To: <20210518064215.2856977-15-tientzu@chromium.org>

Hi Claire,

On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> Introduce the new compatible string, restricted-dma-pool, for restricted
> DMA. One can specify the address and length of the restricted DMA memory
> region by restricted-dma-pool in the reserved-memory node.
> 
> Signed-off-by: Claire Chang <tientzu@chromium.org>
> ---
>  .../reserved-memory/reserved-memory.txt       | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> index e8d3096d922c..284aea659015 100644
> --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> +++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> @@ -51,6 +51,23 @@ compatible (optional) - standard definition
>            used as a shared pool of DMA buffers for a set of devices. It can
>            be used by an operating system to instantiate the necessary pool
>            management subsystem if necessary.
> +        - restricted-dma-pool: This indicates a region of memory meant to be
> +          used as a pool of restricted DMA buffers for a set of devices. The
> +          memory region would be the only region accessible to those devices.
> +          When using this, the no-map and reusable properties must not be set,
> +          so the operating system can create a virtual mapping that will be used
> +          for synchronization. The main purpose for restricted DMA is to
> +          mitigate the lack of DMA access control on systems without an IOMMU,
> +          which could result in the DMA accessing the system memory at
> +          unexpected times and/or unexpected addresses, possibly leading to data
> +          leakage or corruption. The feature on its own provides a basic level
> +          of protection against the DMA overwriting buffer contents at
> +          unexpected times. However, to protect against general data leakage and
> +          system memory corruption, the system needs to provide way to lock down
> +          the memory access, e.g., MPU. Note that since coherent allocation
> +          needs remapping, one must set up another device coherent pool by
> +          shared-dma-pool and use dma_alloc_from_dev_coherent instead for atomic
> +          coherent allocation.
>          - vendor specific string in the form <vendor>,[<device>-]<usage>
>  no-map (optional) - empty property
>      - Indicates the operating system must not create a virtual mapping
> @@ -120,6 +137,11 @@ one for multimedia processing (named multimedia-memory@77000000, 64MiB).
>  			compatible = "acme,multimedia-memory";
>  			reg = <0x77000000 0x4000000>;
>  		};
> +
> +		restricted_dma_mem_reserved: restricted_dma_mem_reserved {
> +			compatible = "restricted-dma-pool";
> +			reg = <0x50000000 0x400000>;
> +		};

nit: You need to update the old text that states "This example defines 3
contiguous regions ...".

>  	};
>  
>  	/* ... */
> @@ -138,4 +160,9 @@ one for multimedia processing (named multimedia-memory@77000000, 64MiB).
>  		memory-region = <&multimedia_reserved>;
>  		/* ... */
>  	};
> +
> +	pcie_device: pcie_device@0,0 {
> +		memory-region = <&restricted_dma_mem_reserved>;
> +		/* ... */
> +	};

I still don't understand how this works for individual PCIe devices -- how
is dev->of_node set to point at the node you have above?

I tried adding the memory-region to the host controller instead, and then
I see it crop up in dmesg:

  | pci-host-generic 40000000.pci: assigned reserved memory node restricted_dma_mem_reserved

but none of the actual PCI devices end up with 'dma_io_tlb_mem' set, and
so the restricted DMA area is not used. In fact, swiotlb isn't used at all.

What am I missing to make this work with PCIe devices?

Thanks,

Will
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2021-05-26 12:13 UTC|newest]

Thread overview: 265+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-18  6:42 [PATCH v7 00/15] Restricted DMA Claire Chang
2021-05-18  6:42 ` [Intel-gfx] " Claire Chang
2021-05-18  6:42 ` Claire Chang
2021-05-18  6:42 ` Claire Chang
2021-05-18  6:42 ` Claire Chang
2021-05-18  6:42 ` [PATCH v7 01/15] swiotlb: Refactor swiotlb init functions Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-19 18:50   ` Florian Fainelli
2021-05-19 18:50     ` [Intel-gfx] " Florian Fainelli
2021-05-19 18:50     ` Florian Fainelli
2021-05-19 18:50     ` Florian Fainelli
2021-05-19 18:50     ` Florian Fainelli
2021-05-20  6:40     ` Claire Chang
2021-05-20  6:40       ` Claire Chang
2021-05-20  6:40       ` [Intel-gfx] " Claire Chang
2021-05-20  6:40       ` Claire Chang
2021-05-20  6:40       ` Claire Chang
2021-05-20  6:40       ` Claire Chang
2021-05-24 15:53       ` Konrad Rzeszutek Wilk
2021-05-24 15:53         ` [Intel-gfx] " Konrad Rzeszutek Wilk
2021-05-24 15:53         ` Konrad Rzeszutek Wilk
2021-05-24 15:53         ` Konrad Rzeszutek Wilk
2021-05-24 15:53         ` Konrad Rzeszutek Wilk
2021-05-25  3:08         ` Claire Chang
2021-05-25  3:08           ` Claire Chang
2021-05-25  3:08           ` [Intel-gfx] " Claire Chang
2021-05-25  3:08           ` Claire Chang
2021-05-25  3:08           ` Claire Chang
2021-05-25  3:08           ` Claire Chang
2021-05-27 13:02     ` Christoph Hellwig
2021-05-27 13:02       ` [Intel-gfx] " Christoph Hellwig
2021-05-27 13:02       ` Christoph Hellwig
2021-05-27 13:02       ` Christoph Hellwig
2021-05-27 14:41       ` Tom Lendacky
2021-05-27 14:41         ` [Intel-gfx] " Tom Lendacky
2021-05-27 14:41         ` Tom Lendacky
2021-05-27 14:41         ` Tom Lendacky
2021-05-27 14:41         ` Tom Lendacky
2021-05-27 16:32         ` Tom Lendacky
2021-05-27 16:32           ` [Intel-gfx] " Tom Lendacky
2021-05-27 16:32           ` Tom Lendacky
2021-05-27 16:32           ` Tom Lendacky
2021-05-27 16:32           ` Tom Lendacky
2021-05-31 15:00           ` Claire Chang
2021-05-31 15:00             ` Claire Chang
2021-05-31 15:00             ` [Intel-gfx] " Claire Chang
2021-05-31 15:00             ` Claire Chang
2021-05-31 15:00             ` Claire Chang
2021-05-31 15:00             ` Claire Chang
2021-05-18  6:42 ` [PATCH v7 02/15] swiotlb: Refactor swiotlb_create_debugfs Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-19 19:24   ` Florian Fainelli
2021-05-19 19:24     ` [Intel-gfx] " Florian Fainelli
2021-05-19 19:24     ` Florian Fainelli
2021-05-19 19:24     ` Florian Fainelli
2021-05-19 19:24     ` Florian Fainelli
2021-05-27 13:24   ` Christoph Hellwig
2021-05-27 13:24     ` [Intel-gfx] " Christoph Hellwig
2021-05-27 13:24     ` Christoph Hellwig
2021-05-27 13:24     ` Christoph Hellwig
2021-05-18  6:42 ` [PATCH v7 03/15] swiotlb: Add DMA_RESTRICTED_POOL Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-19 19:00   ` Florian Fainelli
2021-05-19 19:00     ` [Intel-gfx] " Florian Fainelli
2021-05-19 19:00     ` Florian Fainelli
2021-05-19 19:00     ` Florian Fainelli
2021-05-19 19:00     ` Florian Fainelli
2021-05-27 13:25   ` Christoph Hellwig
2021-05-27 13:25     ` [Intel-gfx] " Christoph Hellwig
2021-05-27 13:25     ` Christoph Hellwig
2021-05-27 13:25     ` Christoph Hellwig
2021-05-18  6:42 ` [PATCH v7 04/15] swiotlb: Add restricted DMA pool initialization Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:48   ` Claire Chang
2021-05-18  6:48     ` Claire Chang
2021-05-18  6:48     ` [Intel-gfx] " Claire Chang
2021-05-18  6:48     ` Claire Chang
2021-05-18  6:48     ` Claire Chang
2021-05-18  6:48     ` Claire Chang
2021-05-24 15:49     ` Konrad Rzeszutek Wilk
2021-05-24 15:49       ` [Intel-gfx] " Konrad Rzeszutek Wilk
2021-05-24 15:49       ` Konrad Rzeszutek Wilk
2021-05-24 15:49       ` Konrad Rzeszutek Wilk
2021-05-24 15:49       ` Konrad Rzeszutek Wilk
2021-05-25  3:08       ` Claire Chang
2021-05-25  3:08         ` Claire Chang
2021-05-25  3:08         ` [Intel-gfx] " Claire Chang
2021-05-25  3:08         ` Claire Chang
2021-05-25  3:08         ` Claire Chang
2021-05-25  3:08         ` Claire Chang
2021-05-27 13:27       ` Christoph Hellwig
2021-05-27 13:27         ` [Intel-gfx] " Christoph Hellwig
2021-05-27 13:27         ` Christoph Hellwig
2021-05-27 13:27         ` Christoph Hellwig
2021-05-19 18:54   ` Florian Fainelli
2021-05-19 18:54     ` [Intel-gfx] " Florian Fainelli
2021-05-19 18:54     ` Florian Fainelli
2021-05-19 18:54     ` Florian Fainelli
2021-05-19 18:54     ` Florian Fainelli
2021-05-20  6:39     ` Claire Chang
2021-05-20  6:39       ` Claire Chang
2021-05-20  6:39       ` [Intel-gfx] " Claire Chang
2021-05-20  6:39       ` Claire Chang
2021-05-20  6:39       ` Claire Chang
2021-05-20  6:39       ` Claire Chang
2021-05-27 13:27   ` Christoph Hellwig
2021-05-27 13:27     ` [Intel-gfx] " Christoph Hellwig
2021-05-27 13:27     ` Christoph Hellwig
2021-05-27 13:27     ` Christoph Hellwig
2021-05-18  6:42 ` [PATCH v7 05/15] swiotlb: Add a new get_io_tlb_mem getter Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:51   ` Claire Chang
2021-05-18  6:51     ` Claire Chang
2021-05-18  6:51     ` [Intel-gfx] " Claire Chang
2021-05-18  6:51     ` Claire Chang
2021-05-18  6:51     ` Claire Chang
2021-05-18  6:51     ` Claire Chang
2021-05-24 15:51     ` Konrad Rzeszutek Wilk
2021-05-24 15:51       ` [Intel-gfx] " Konrad Rzeszutek Wilk
2021-05-24 15:51       ` Konrad Rzeszutek Wilk
2021-05-24 15:51       ` Konrad Rzeszutek Wilk
2021-05-24 15:51       ` Konrad Rzeszutek Wilk
2021-05-25  3:08       ` Claire Chang
2021-05-25  3:08         ` Claire Chang
2021-05-25  3:08         ` [Intel-gfx] " Claire Chang
2021-05-25  3:08         ` Claire Chang
2021-05-25  3:08         ` Claire Chang
2021-05-25  3:08         ` Claire Chang
2021-05-19 19:18   ` Florian Fainelli
2021-05-19 19:18     ` [Intel-gfx] " Florian Fainelli
2021-05-19 19:18     ` Florian Fainelli
2021-05-19 19:18     ` Florian Fainelli
2021-05-19 19:18     ` Florian Fainelli
2021-05-18  6:42 ` [PATCH v7 06/15] swiotlb: Update is_swiotlb_buffer to add a struct device argument Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-19 19:19   ` Florian Fainelli
2021-05-19 19:19     ` [Intel-gfx] " Florian Fainelli
2021-05-19 19:19     ` Florian Fainelli
2021-05-19 19:19     ` Florian Fainelli
2021-05-19 19:19     ` Florian Fainelli
2021-05-18  6:42 ` [PATCH v7 07/15] swiotlb: Update is_swiotlb_active " Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-19 19:20   ` Florian Fainelli
2021-05-19 19:20     ` [Intel-gfx] " Florian Fainelli
2021-05-19 19:20     ` Florian Fainelli
2021-05-19 19:20     ` Florian Fainelli
2021-05-19 19:20     ` Florian Fainelli
2021-05-27 13:28   ` Christoph Hellwig
2021-05-27 13:28     ` [Intel-gfx] " Christoph Hellwig
2021-05-27 13:28     ` Christoph Hellwig
2021-05-27 13:28     ` Christoph Hellwig
2021-05-18  6:42 ` [PATCH v7 08/15] swiotlb: Bounce data from/to restricted DMA pool if available Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42 ` [PATCH v7 09/15] swiotlb: Move alloc_size to find_slots Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42 ` [PATCH v7 10/15] swiotlb: Refactor swiotlb_tbl_unmap_single Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42 ` [PATCH v7 11/15] dma-direct: Add a new wrapper __dma_direct_free_pages() Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-19 18:59   ` Florian Fainelli
2021-05-19 18:59     ` [Intel-gfx] " Florian Fainelli
2021-05-19 18:59     ` Florian Fainelli
2021-05-19 18:59     ` Florian Fainelli
2021-05-19 18:59     ` Florian Fainelli
2021-05-18  6:42 ` [PATCH v7 12/15] swiotlb: Add restricted DMA alloc/free support Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42 ` [PATCH v7 13/15] dma-direct: Allocate memory from restricted DMA pool if available Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-27 13:30   ` Christoph Hellwig
2021-05-27 13:30     ` [Intel-gfx] " Christoph Hellwig
2021-05-27 13:30     ` Christoph Hellwig
2021-05-27 13:30     ` Christoph Hellwig
2021-05-18  6:42 ` [PATCH v7 14/15] dt-bindings: of: Add restricted DMA pool Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-26 12:13   ` Will Deacon [this message]
2021-05-26 12:13     ` [Intel-gfx] " Will Deacon
2021-05-26 12:13     ` Will Deacon
2021-05-26 12:13     ` Will Deacon
2021-05-26 12:13     ` Will Deacon
2021-05-26 15:53     ` Will Deacon
2021-05-26 15:53       ` [Intel-gfx] " Will Deacon
2021-05-26 15:53       ` Will Deacon
2021-05-26 15:53       ` Will Deacon
2021-05-26 15:53       ` Will Deacon
2021-05-27 11:29       ` Claire Chang
2021-05-27 11:29         ` Claire Chang
2021-05-27 11:29         ` [Intel-gfx] " Claire Chang
2021-05-27 11:29         ` Claire Chang
2021-05-27 11:29         ` Claire Chang
2021-05-27 11:29         ` Claire Chang
2021-05-27 11:34         ` Will Deacon
2021-05-27 11:34           ` [Intel-gfx] " Will Deacon
2021-05-27 11:34           ` Will Deacon
2021-05-27 11:34           ` Will Deacon
2021-05-27 11:34           ` Will Deacon
2021-05-27 12:48           ` Claire Chang
2021-05-27 12:48             ` Claire Chang
2021-05-27 12:48             ` [Intel-gfx] " Claire Chang
2021-05-27 12:48             ` Claire Chang
2021-05-27 12:48             ` Claire Chang
2021-05-27 12:48             ` Claire Chang
2021-05-27 12:53             ` Will Deacon
2021-05-27 12:53               ` [Intel-gfx] " Will Deacon
2021-05-27 12:53               ` Will Deacon
2021-05-27 12:53               ` Will Deacon
2021-05-27 12:53               ` Will Deacon
2021-05-18  6:42 ` [PATCH v7 15/15] of: Add plumbing for " Claire Chang
2021-05-18  6:42   ` [Intel-gfx] " Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:42   ` Claire Chang
2021-05-18  6:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Restricted DMA (rev3) Patchwork
2021-05-18  6:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-18  7:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-18  9:10 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-05-27 13:00 ` [PATCH v7 00/15] Restricted DMA Claire Chang
2021-05-27 13:00   ` Claire Chang
2021-05-27 13:00   ` [Intel-gfx] " Claire Chang
2021-05-27 13:00   ` Claire Chang
2021-05-27 13:00   ` Claire Chang
2021-05-27 13:00   ` Claire Chang
2021-05-27 13:54 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Restricted DMA (rev4) Patchwork
2021-06-01 19:42 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Restricted DMA (rev5) Patchwork

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