Re: [PATCH v7 3/4] dt-bindings: firmware: Add bindings for xilinx firmware

From: Rob Herring <robh@kernel.org>
To: Nava kishore Manne <nava.manne@xilinx.com>
Cc: michal.simek@xilinx.com, mdf@kernel.org, trix@redhat.com,
	arnd@arndb.de, rajan.vaja@xilinx.com, gregkh@linuxfoundation.org,
	amit.sunil.dhamne@xilinx.com, tejas.patel@xilinx.com,
	zou_wei@huawei.com, lakshmi.sai.krishna.potthuri@xilinx.com,
	ravi.patel@xilinx.com, iwamatsu@nigauri.org,
	wendy.liang@xilinx.com, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org,
	git@xilinx.com, chinnikishore369@gmail.com
Subject: Re: [PATCH v7 3/4] dt-bindings: firmware: Add bindings for xilinx firmware
Date: Thu, 10 Jun 2021 11:03:42 -0500	[thread overview]
Message-ID: <20210610160342.GA1883933@robh.at.kernel.org> (raw)
In-Reply-To: <20210604113332.1394-4-nava.manne@xilinx.com>

On Fri, Jun 04, 2021 at 05:03:31PM +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx firmware driver bindings.
> Firmware driver provides an interface to firmware APIs.
> Interface APIs can be used by any driver to communicate
> to Platform Management Unit.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v4:
>               -Added new yaml file for xilinx firmware
>                as suggested by Rob.
> 
> Changes for v5:
>               -Fixed some minor issues and updated the fpga node name to versal_fpga.
> 
> Changes for v6:
>               -Added AES and Clk nodes as a sub nodes to the firmware node.
> 
> Changes for v7:
>               -Fixed child nodes format ssues.
> 
>  .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 94 +++++++++++++++++++
>  1 file changed, 94 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml

You need to remove xlnx,zynqmp-firmware.txt

> 
> diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> new file mode 100644
> index 000000000000..8e0241c4c137
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx firmware driver
> +
> +maintainers:
> +  - Nava kishore Manne <nava.manne@xilinx.com>
> +
> +description:
> +  The zynqmp-firmware node describes the interface to platform firmware.
> +  ZynqMP has an interface to communicate with secure firmware. Firmware
> +  driver provides an interface to firmware APIs. Interface APIs can be
> +  used by any driver to communicate to PMUFW(Platform Management Unit).
> +  These requests include clock management, pin control, device control,
> +  power management service, FPGA service and other platform management
> +  services.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - description:
> +          For implementations complying for Zynq Ultrascale+ MPSoC.
> +        const: xlnx,zynqmp-firmware
> +
> +      - description:
> +          For implementations complying for Versal.
> +        const: xlnx,versal-firmware
> +
> +  method:
> +    description: |
> +                 The method of calling the PM-API firmware layer.
> +                 Permitted values are.
> +                 - "smc" : SMC #0, following the SMCCC
> +                 - "hvc" : HVC #0, following the SMCCC
> +
> +    $ref: /schemas/types.yaml#/definitions/string-array
> +    enum:
> +      - smc
> +      - hvc
> +
> +  "versal_fpga":

Don't need quotes

> +    $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
> +    description: Compatible of the FPGA device.
> +    type: object
> +
> +  "zynqmp-aes":

Don't need quotes

> +    $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
> +    description: |
> +                 The ZynqMP AES-GCM hardened cryptographic accelerator is
> +                 used to encrypt or decrypt the data with provided key and
> +                 initialization vector.

Don't need '|' here (there's no formatting) and indent 2 more than 
'description'.

> +    type: object
> +
> +  "clock-controller":
> +    $ref: /schemas/clock/xlnx,versal-clk.yaml#
> +    description: |
> +                 The clock controller is a hardware block of Xilinx versal
> +                 clock tree. It reads required input clock frequencies from
> +                 the devicetree and acts as clock provider for all clock
> +                 consumers of PS clocks.list of clock specifiers which are
> +                 external input clocks to the given clock controller.
> +    type: object
> +
> +required:
> +  - compatible
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    versal-firmware {
> +      compatible = "xlnx,versal-firmware";
> +      method = "smc";
> +
> +      versal_fpga: versal_fpga {
> +        compatible = "xlnx,versal-fpga";
> +      };
> +
> +      xlnx_aes: zynqmp-aes {
> +        compatible = "xlnx,zynqmp-aes";
> +      };
> +
> +      versal_clk: clock-controller {
> +        #clock-cells = <1>;
> +        compatible = "xlnx,versal-clk";
> +        clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
> +        clock-names = "ref", "alt_ref", "pl_alt_ref";
> +      };
> +    };
> +
> +...
> -- 
> 2.17.1