From: Anup Patel <anup.patel@wdc.com> To: Peter Maydell <peter.maydell@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Atish Patra <atish.patra@wdc.com>, Anup Patel <anup.patel@wdc.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel <anup@brainfault.org> Subject: [PATCH v1 0/3] RISC-V ACLINT Support Date: Sat, 12 Jun 2021 21:36:12 +0530 [thread overview] Message-ID: <20210612160615.330768-1-anup.patel@wdc.com> (raw) The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement over the SiFive CLINT but also maintains backward compatibility with the SiFive CLINT. Latest RISC-V ACLINT specification (will be frozen in a month) can be found at: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc This series: 1) Replaces SiFive CLINT implementation with RISC-V ACLINT 2) Refactors RISC-V virt machine FDT generation 3) Adds optional full ACLINT support in QEMU RISC-V virt machine This series can be found in the riscv_aclint_v1 branch at: https://github.com/avpatel/qemu.git To test series, we require OpenSBI and Linux with ACLINT support which can be found in riscv_aclint_v1 branch at: https://github.com/avpatel/opensbi.git https://github.com/avpatel/linux.git Anup Patel (3): hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT hw/riscv: virt: Re-factor FDT generation hw/riscv: virt: Add optional ACLINT support to virt machine hw/intc/Kconfig | 2 +- hw/intc/meson.build | 2 +- hw/intc/riscv_aclint.c | 374 +++++++++++++++++++ hw/intc/sifive_clint.c | 266 -------------- hw/riscv/Kconfig | 10 +- hw/riscv/microchip_pfsoc.c | 12 +- hw/riscv/sifive_e.c | 12 +- hw/riscv/sifive_u.c | 14 +- hw/riscv/spike.c | 15 +- hw/riscv/virt.c | 635 ++++++++++++++++++++++----------- include/hw/intc/riscv_aclint.h | 73 ++++ include/hw/intc/sifive_clint.h | 60 ---- include/hw/riscv/virt.h | 2 + 13 files changed, 923 insertions(+), 554 deletions(-) create mode 100644 hw/intc/riscv_aclint.c delete mode 100644 hw/intc/sifive_clint.c create mode 100644 include/hw/intc/riscv_aclint.h delete mode 100644 include/hw/intc/sifive_clint.h -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup.patel@wdc.com> To: Peter Maydell <peter.maydell@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Atish Patra <atish.patra@wdc.com>, Anup Patel <anup@brainfault.org>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel <anup.patel@wdc.com> Subject: [PATCH v1 0/3] RISC-V ACLINT Support Date: Sat, 12 Jun 2021 21:36:12 +0530 [thread overview] Message-ID: <20210612160615.330768-1-anup.patel@wdc.com> (raw) The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement over the SiFive CLINT but also maintains backward compatibility with the SiFive CLINT. Latest RISC-V ACLINT specification (will be frozen in a month) can be found at: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc This series: 1) Replaces SiFive CLINT implementation with RISC-V ACLINT 2) Refactors RISC-V virt machine FDT generation 3) Adds optional full ACLINT support in QEMU RISC-V virt machine This series can be found in the riscv_aclint_v1 branch at: https://github.com/avpatel/qemu.git To test series, we require OpenSBI and Linux with ACLINT support which can be found in riscv_aclint_v1 branch at: https://github.com/avpatel/opensbi.git https://github.com/avpatel/linux.git Anup Patel (3): hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT hw/riscv: virt: Re-factor FDT generation hw/riscv: virt: Add optional ACLINT support to virt machine hw/intc/Kconfig | 2 +- hw/intc/meson.build | 2 +- hw/intc/riscv_aclint.c | 374 +++++++++++++++++++ hw/intc/sifive_clint.c | 266 -------------- hw/riscv/Kconfig | 10 +- hw/riscv/microchip_pfsoc.c | 12 +- hw/riscv/sifive_e.c | 12 +- hw/riscv/sifive_u.c | 14 +- hw/riscv/spike.c | 15 +- hw/riscv/virt.c | 635 ++++++++++++++++++++++----------- include/hw/intc/riscv_aclint.h | 73 ++++ include/hw/intc/sifive_clint.h | 60 ---- include/hw/riscv/virt.h | 2 + 13 files changed, 923 insertions(+), 554 deletions(-) create mode 100644 hw/intc/riscv_aclint.c delete mode 100644 hw/intc/sifive_clint.c create mode 100644 include/hw/intc/riscv_aclint.h delete mode 100644 include/hw/intc/sifive_clint.h -- 2.25.1
next reply other threads:[~2021-06-12 16:13 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-12 16:06 Anup Patel [this message] 2021-06-12 16:06 ` [PATCH v1 0/3] RISC-V ACLINT Support Anup Patel 2021-06-12 16:06 ` [PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Anup Patel 2021-06-12 16:06 ` Anup Patel 2021-06-14 12:22 ` Bin Meng 2021-06-14 12:22 ` Bin Meng 2021-07-12 5:00 ` Anup Patel 2021-07-12 5:00 ` Anup Patel 2021-06-18 6:50 ` Alistair Francis 2021-06-18 6:50 ` Alistair Francis 2021-07-12 5:32 ` Anup Patel 2021-07-12 5:32 ` Anup Patel 2021-06-12 16:06 ` [PATCH v1 2/3] hw/riscv: virt: Re-factor FDT generation Anup Patel 2021-06-12 16:06 ` Anup Patel 2021-06-14 12:22 ` Bin Meng 2021-06-14 12:22 ` Bin Meng 2021-07-12 5:40 ` Anup Patel 2021-07-12 5:40 ` Anup Patel 2021-06-12 16:06 ` [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine Anup Patel 2021-06-12 16:06 ` Anup Patel 2021-06-14 12:22 ` Bin Meng 2021-06-14 12:22 ` Bin Meng 2021-07-12 5:38 ` Anup Patel 2021-07-12 5:38 ` Anup Patel 2021-07-12 6:15 ` Bin Meng 2021-07-12 6:15 ` Bin Meng 2021-07-12 10:53 ` Anup Patel 2021-07-12 10:53 ` Anup Patel 2021-07-12 13:11 ` Bin Meng 2021-07-12 13:11 ` Bin Meng 2021-07-12 15:02 ` Anup Patel 2021-07-12 15:02 ` Anup Patel 2021-07-12 23:05 ` Bin Meng 2021-07-12 23:05 ` Bin Meng
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