From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions Date: Thu, 24 Jun 2021 18:54:56 +0800 [thread overview] Message-ID: <20210624105521.3964-13-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> Instructions include signed or unsigned minimum, maximum, clip value, absolute value, and leading zero, leading one count instructions. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/helper.h | 12 +++ target/riscv/insn32.decode | 12 +++ target/riscv/insn_trans/trans_rvp.c.inc | 13 +++ target/riscv/packed_helper.c | 115 ++++++++++++++++++++++++ 4 files changed, 152 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 88035aafad..240df8b766 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1243,3 +1243,15 @@ DEF_HELPER_2(kabs16, tl, env, tl) DEF_HELPER_2(clrs16, tl, env, tl) DEF_HELPER_2(clz16, tl, env, tl) DEF_HELPER_2(clo16, tl, env, tl) + +DEF_HELPER_3(smin8, tl, env, tl, tl) +DEF_HELPER_3(umin8, tl, env, tl, tl) +DEF_HELPER_3(smax8, tl, env, tl, tl) +DEF_HELPER_3(umax8, tl, env, tl, tl) +DEF_HELPER_3(sclip8, tl, env, tl, tl) +DEF_HELPER_3(uclip8, tl, env, tl, tl) +DEF_HELPER_2(kabs8, tl, env, tl) +DEF_HELPER_2(clrs8, tl, env, tl) +DEF_HELPER_2(clz8, tl, env, tl) +DEF_HELPER_2(clo8, tl, env, tl) +DEF_HELPER_2(swap8, tl, env, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 847c796874..4c34f0f4f4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -846,3 +846,15 @@ kabs16 1010110 10001 ..... 000 ..... 1110111 @r2 clrs16 1010111 01000 ..... 000 ..... 1110111 @r2 clz16 1010111 01001 ..... 000 ..... 1110111 @r2 clo16 1010111 01011 ..... 000 ..... 1110111 @r2 + +smin8 1000100 ..... ..... 000 ..... 1110111 @r +umin8 1001100 ..... ..... 000 ..... 1110111 @r +smax8 1000101 ..... ..... 000 ..... 1110111 @r +umax8 1001101 ..... ..... 000 ..... 1110111 @r +sclip8 1000110 00... ..... 000 ..... 1110111 @sh3 +uclip8 1000110 10... ..... 000 ..... 1110111 @sh3 +kabs8 1010110 10000 ..... 000 ..... 1110111 @r2 +clrs8 1010111 00000 ..... 000 ..... 1110111 @r2 +clz8 1010111 00001 ..... 000 ..... 1110111 @r2 +clo8 1010111 00011 ..... 000 ..... 1110111 @r2 +swap8 1010110 11000 ..... 000 ..... 1110111 @r2 diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 3e6307cdc3..c5ec530fd7 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -335,3 +335,16 @@ GEN_RVP_R2_OOL(kabs16); GEN_RVP_R2_OOL(clrs16); GEN_RVP_R2_OOL(clz16); GEN_RVP_R2_OOL(clo16); + +/* SIMD 8-bit Miscellaneous Instructions */ +GEN_RVP_R_OOL(smin8); +GEN_RVP_R_OOL(umin8); +GEN_RVP_R_OOL(smax8); +GEN_RVP_R_OOL(umax8); +GEN_RVP_SHIFTI(sclip8, NULL, gen_helper_sclip8); +GEN_RVP_SHIFTI(uclip8, NULL, gen_helper_uclip8); +GEN_RVP_R2_OOL(kabs8); +GEN_RVP_R2_OOL(clrs8); +GEN_RVP_R2_OOL(clz8); +GEN_RVP_R2_OOL(clo8); +GEN_RVP_R2_OOL(swap8); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index e4a9463135..3d3d2bf3e4 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -1078,3 +1078,118 @@ static inline void do_clo16(CPURISCVState *env, void *vd, void *va, uint8_t i) } RVPR2(clo16, 1, 2); + +/* SIMD 8-bit Miscellaneous Instructions */ +static inline void do_smin8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] < b[i]) ? a[i] : b[i]; +} + +RVPR(smin8, 1, 1); + +static inline void do_umin8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint8_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] < b[i]) ? a[i] : b[i]; +} + +RVPR(umin8, 1, 1); + +static inline void do_smax8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] > b[i]) ? a[i] : b[i]; +} + +RVPR(smax8, 1, 1); + +static inline void do_umax8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint8_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] > b[i]) ? a[i] : b[i]; +} + +RVPR(umax8, 1, 1); + +static inline void do_sclip8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x7; + + d[i] = sat64(env, a[i], shift); +} + +RVPR(sclip8, 1, 1); + +static inline void do_uclip8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x7; + + if (a[i] < 0) { + d[i] = 0; + env->vxsat = 0x1; + } else { + d[i] = satu64(env, a[i], shift); + } +} + +RVPR(uclip8, 1, 1); + +static inline void do_kabs8(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int8_t *d = vd, *a = va; + + if (a[i] == INT8_MIN) { + d[i] = INT8_MAX; + env->vxsat = 0x1; + } else { + d[i] = abs(a[i]); + } +} + +RVPR2(kabs8, 1, 1); + +static inline void do_clrs8(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int8_t *d = vd, *a = va; + d[i] = clrsb32(a[i]) - 24; +} + +RVPR2(clrs8, 1, 1); + +static inline void do_clz8(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int8_t *d = vd, *a = va; + d[i] = (a[i] < 0) ? 0 : (clz32(a[i]) - 24); +} + +RVPR2(clz8, 1, 1); + +static inline void do_clo8(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int8_t *d = vd, *a = va; + d[i] = (a[i] >= 0) ? 0 : (clo32(a[i]) - 24); +} + +RVPR2(clo8, 1, 1); + +static inline void do_swap8(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int8_t *d = vd, *a = va; + d[H1(i)] = a[H1(i + 1)]; + d[H1(i + 1)] = a[H1(i)]; +} + +RVPR2(swap8, 2, 1); -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions Date: Thu, 24 Jun 2021 18:54:56 +0800 [thread overview] Message-ID: <20210624105521.3964-13-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> Instructions include signed or unsigned minimum, maximum, clip value, absolute value, and leading zero, leading one count instructions. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/helper.h | 12 +++ target/riscv/insn32.decode | 12 +++ target/riscv/insn_trans/trans_rvp.c.inc | 13 +++ target/riscv/packed_helper.c | 115 ++++++++++++++++++++++++ 4 files changed, 152 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 88035aafad..240df8b766 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1243,3 +1243,15 @@ DEF_HELPER_2(kabs16, tl, env, tl) DEF_HELPER_2(clrs16, tl, env, tl) DEF_HELPER_2(clz16, tl, env, tl) DEF_HELPER_2(clo16, tl, env, tl) + +DEF_HELPER_3(smin8, tl, env, tl, tl) +DEF_HELPER_3(umin8, tl, env, tl, tl) +DEF_HELPER_3(smax8, tl, env, tl, tl) +DEF_HELPER_3(umax8, tl, env, tl, tl) +DEF_HELPER_3(sclip8, tl, env, tl, tl) +DEF_HELPER_3(uclip8, tl, env, tl, tl) +DEF_HELPER_2(kabs8, tl, env, tl) +DEF_HELPER_2(clrs8, tl, env, tl) +DEF_HELPER_2(clz8, tl, env, tl) +DEF_HELPER_2(clo8, tl, env, tl) +DEF_HELPER_2(swap8, tl, env, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 847c796874..4c34f0f4f4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -846,3 +846,15 @@ kabs16 1010110 10001 ..... 000 ..... 1110111 @r2 clrs16 1010111 01000 ..... 000 ..... 1110111 @r2 clz16 1010111 01001 ..... 000 ..... 1110111 @r2 clo16 1010111 01011 ..... 000 ..... 1110111 @r2 + +smin8 1000100 ..... ..... 000 ..... 1110111 @r +umin8 1001100 ..... ..... 000 ..... 1110111 @r +smax8 1000101 ..... ..... 000 ..... 1110111 @r +umax8 1001101 ..... ..... 000 ..... 1110111 @r +sclip8 1000110 00... ..... 000 ..... 1110111 @sh3 +uclip8 1000110 10... ..... 000 ..... 1110111 @sh3 +kabs8 1010110 10000 ..... 000 ..... 1110111 @r2 +clrs8 1010111 00000 ..... 000 ..... 1110111 @r2 +clz8 1010111 00001 ..... 000 ..... 1110111 @r2 +clo8 1010111 00011 ..... 000 ..... 1110111 @r2 +swap8 1010110 11000 ..... 000 ..... 1110111 @r2 diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 3e6307cdc3..c5ec530fd7 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -335,3 +335,16 @@ GEN_RVP_R2_OOL(kabs16); GEN_RVP_R2_OOL(clrs16); GEN_RVP_R2_OOL(clz16); GEN_RVP_R2_OOL(clo16); + +/* SIMD 8-bit Miscellaneous Instructions */ +GEN_RVP_R_OOL(smin8); +GEN_RVP_R_OOL(umin8); +GEN_RVP_R_OOL(smax8); +GEN_RVP_R_OOL(umax8); +GEN_RVP_SHIFTI(sclip8, NULL, gen_helper_sclip8); +GEN_RVP_SHIFTI(uclip8, NULL, gen_helper_uclip8); +GEN_RVP_R2_OOL(kabs8); +GEN_RVP_R2_OOL(clrs8); +GEN_RVP_R2_OOL(clz8); +GEN_RVP_R2_OOL(clo8); +GEN_RVP_R2_OOL(swap8); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index e4a9463135..3d3d2bf3e4 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -1078,3 +1078,118 @@ static inline void do_clo16(CPURISCVState *env, void *vd, void *va, uint8_t i) } RVPR2(clo16, 1, 2); + +/* SIMD 8-bit Miscellaneous Instructions */ +static inline void do_smin8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] < b[i]) ? a[i] : b[i]; +} + +RVPR(smin8, 1, 1); + +static inline void do_umin8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint8_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] < b[i]) ? a[i] : b[i]; +} + +RVPR(umin8, 1, 1); + +static inline void do_smax8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] > b[i]) ? a[i] : b[i]; +} + +RVPR(smax8, 1, 1); + +static inline void do_umax8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint8_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] > b[i]) ? a[i] : b[i]; +} + +RVPR(umax8, 1, 1); + +static inline void do_sclip8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x7; + + d[i] = sat64(env, a[i], shift); +} + +RVPR(sclip8, 1, 1); + +static inline void do_uclip8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x7; + + if (a[i] < 0) { + d[i] = 0; + env->vxsat = 0x1; + } else { + d[i] = satu64(env, a[i], shift); + } +} + +RVPR(uclip8, 1, 1); + +static inline void do_kabs8(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int8_t *d = vd, *a = va; + + if (a[i] == INT8_MIN) { + d[i] = INT8_MAX; + env->vxsat = 0x1; + } else { + d[i] = abs(a[i]); + } +} + +RVPR2(kabs8, 1, 1); + +static inline void do_clrs8(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int8_t *d = vd, *a = va; + d[i] = clrsb32(a[i]) - 24; +} + +RVPR2(clrs8, 1, 1); + +static inline void do_clz8(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int8_t *d = vd, *a = va; + d[i] = (a[i] < 0) ? 0 : (clz32(a[i]) - 24); +} + +RVPR2(clz8, 1, 1); + +static inline void do_clo8(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int8_t *d = vd, *a = va; + d[i] = (a[i] >= 0) ? 0 : (clo32(a[i]) - 24); +} + +RVPR2(clo8, 1, 1); + +static inline void do_swap8(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int8_t *d = vd, *a = va; + d[H1(i)] = a[H1(i + 1)]; + d[H1(i + 1)] = a[H1(i)]; +} + +RVPR2(swap8, 2, 1); -- 2.17.1
next prev parent reply other threads:[~2021-06-24 11:28 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-24 10:54 [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-07-01 2:02 ` Alistair Francis 2021-07-01 2:02 ` Alistair Francis 2021-06-24 10:54 ` [PATCH v3 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-07-01 2:08 ` Alistair Francis 2021-07-01 2:08 ` Alistair Francis 2021-06-24 10:54 ` [PATCH v3 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei [this message] 2021-06-24 10:54 ` [PATCH v3 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 11:55 ` [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 no-reply 2021-06-24 11:55 ` no-reply 2021-07-01 1:30 ` Alistair Francis 2021-07-01 1:30 ` Alistair Francis 2021-07-01 3:06 ` LIU Zhiwei 2021-07-01 3:06 ` LIU Zhiwei
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