From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: John Harrison <John.C.Harrison@Intel.com>, dri-devel@lists.freedesktop.org Subject: [PATCH 30/53] drm/i915/dg2: Maintain backward-compatible nested batch behavior Date: Thu, 1 Jul 2021 13:24:04 -0700 [thread overview] Message-ID: <20210701202427.1547543-31-matthew.d.roper@intel.com> (raw) In-Reply-To: <20210701202427.1547543-1-matthew.d.roper@intel.com> For tgl+, the per-context setting of MI_MODE[12] determines whether the bits of a nested MI_BATCH_BUFFER_START instruction should be interpreted in the traditional manner or whether they should instead use a new tgl+ meaning that breaks backward compatibility, but allows nesting into 3rd-level batchbuffers. For previous platforms, the hardware default for this register bit is to maintain backward-compatible behavior unless a context intentionally opts into the new behavior; however Xe_HPG flips the hardware default behavior. From a SW perspective, we want to maintain the backward-compatible behavior for userspace, so we'll apply a fake workaround to set it back to the legacy behavior on platforms where the hardware default is to break compatibility. At the moment there is no Linux userspace that utilizes third-level batchbuffers, so this will avoid userspace from needing to make any changes. using the legacy meaning is the correct thing to do. If/when we have userspace consumers that want to utilize third-level batch nesting, we can provide a context parameter to allow them to opt-in. Bspec: 45974, 45718 Cc: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 +++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index f97ff2848122..43db766b0672 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -686,6 +686,37 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); } +static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + /* + * This is a "fake" workaround defined by software to ensure we + * maintain reliable, backward-compatible behavior for userspace with + * regards to how nested MI_BATCH_BUFFER_START commands are handled. + * + * The per-context setting of MI_MODE[12] determines whether the bits + * of a nested MI_BATCH_BUFFER_START instruction should be interpreted + * in the traditional manner or whether they should instead use a new + * tgl+ meaning that breaks backward compatibility, but allows nesting + * into 3rd-level batchbuffers. When this new capability was first + * added in TGL, it remained off by default unless a context + * intentionally opted in to the new behavior. However Xe_HPG now + * flips this on by default and requires that we explicitly opt out if + * we don't want the new behavior. + * + * From a SW perspective, we want to maintain the backward-compatible + * behavior for userspace, so we'll apply a fake workaround to set it + * back to the legacy behavior on platforms where the hardware default + * is to break compatibility. At the moment there is no Linux + * userspace that utilizes third-level batchbuffers, so this will avoid + * userspace from needing to make any changes. using the legacy + * meaning is the correct thing to do. If/when we have userspace + * consumers that want to utilize third-level batch nesting, we can + * provide a context parameter to allow them to opt-in. + */ + wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); +} + static void __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, struct i915_wa_list *wal, @@ -693,11 +724,15 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, { struct drm_i915_private *i915 = engine->i915; + wa_init_start(wal, name, engine->name); + + /* Applies to all engines */ + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) + fakewa_disable_nestedbb_mode(engine, wal); + if (engine->class != RENDER_CLASS) return; - wa_init_start(wal, name, engine->name); - if (IS_DG1(i915)) dg1_ctx_workarounds_init(engine, wal); else if (GRAPHICS_VER(i915) == 12) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b19d102e0a01..35a42df1f2aa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2821,6 +2821,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define MI_MODE _MMIO(0x209c) # define VS_TIMER_DISPATCH (1 << 6) # define MI_FLUSH_ENABLE (1 << 12) +# define TGL_NESTED_BB_EN (1 << 12) # define ASYNC_FLIP_PERF_DISABLE (1 << 14) # define MODE_IDLE (1 << 9) # define STOP_RING (1 << 8) -- 2.25.4
WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 30/53] drm/i915/dg2: Maintain backward-compatible nested batch behavior Date: Thu, 1 Jul 2021 13:24:04 -0700 [thread overview] Message-ID: <20210701202427.1547543-31-matthew.d.roper@intel.com> (raw) In-Reply-To: <20210701202427.1547543-1-matthew.d.roper@intel.com> For tgl+, the per-context setting of MI_MODE[12] determines whether the bits of a nested MI_BATCH_BUFFER_START instruction should be interpreted in the traditional manner or whether they should instead use a new tgl+ meaning that breaks backward compatibility, but allows nesting into 3rd-level batchbuffers. For previous platforms, the hardware default for this register bit is to maintain backward-compatible behavior unless a context intentionally opts into the new behavior; however Xe_HPG flips the hardware default behavior. From a SW perspective, we want to maintain the backward-compatible behavior for userspace, so we'll apply a fake workaround to set it back to the legacy behavior on platforms where the hardware default is to break compatibility. At the moment there is no Linux userspace that utilizes third-level batchbuffers, so this will avoid userspace from needing to make any changes. using the legacy meaning is the correct thing to do. If/when we have userspace consumers that want to utilize third-level batch nesting, we can provide a context parameter to allow them to opt-in. Bspec: 45974, 45718 Cc: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 +++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index f97ff2848122..43db766b0672 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -686,6 +686,37 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); } +static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + /* + * This is a "fake" workaround defined by software to ensure we + * maintain reliable, backward-compatible behavior for userspace with + * regards to how nested MI_BATCH_BUFFER_START commands are handled. + * + * The per-context setting of MI_MODE[12] determines whether the bits + * of a nested MI_BATCH_BUFFER_START instruction should be interpreted + * in the traditional manner or whether they should instead use a new + * tgl+ meaning that breaks backward compatibility, but allows nesting + * into 3rd-level batchbuffers. When this new capability was first + * added in TGL, it remained off by default unless a context + * intentionally opted in to the new behavior. However Xe_HPG now + * flips this on by default and requires that we explicitly opt out if + * we don't want the new behavior. + * + * From a SW perspective, we want to maintain the backward-compatible + * behavior for userspace, so we'll apply a fake workaround to set it + * back to the legacy behavior on platforms where the hardware default + * is to break compatibility. At the moment there is no Linux + * userspace that utilizes third-level batchbuffers, so this will avoid + * userspace from needing to make any changes. using the legacy + * meaning is the correct thing to do. If/when we have userspace + * consumers that want to utilize third-level batch nesting, we can + * provide a context parameter to allow them to opt-in. + */ + wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); +} + static void __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, struct i915_wa_list *wal, @@ -693,11 +724,15 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, { struct drm_i915_private *i915 = engine->i915; + wa_init_start(wal, name, engine->name); + + /* Applies to all engines */ + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) + fakewa_disable_nestedbb_mode(engine, wal); + if (engine->class != RENDER_CLASS) return; - wa_init_start(wal, name, engine->name); - if (IS_DG1(i915)) dg1_ctx_workarounds_init(engine, wal); else if (GRAPHICS_VER(i915) == 12) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b19d102e0a01..35a42df1f2aa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2821,6 +2821,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define MI_MODE _MMIO(0x209c) # define VS_TIMER_DISPATCH (1 << 6) # define MI_FLUSH_ENABLE (1 << 12) +# define TGL_NESTED_BB_EN (1 << 12) # define ASYNC_FLIP_PERF_DISABLE (1 << 14) # define MODE_IDLE (1 << 9) # define STOP_RING (1 << 8) -- 2.25.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-01 20:26 UTC|newest] Thread overview: 173+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-01 20:23 [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 01/53] drm/i915: Add "release id" version Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-02 12:33 ` Tvrtko Ursulin 2021-07-02 12:33 ` Tvrtko Ursulin 2021-07-05 11:52 ` Jani Nikula 2021-07-05 11:52 ` Jani Nikula 2021-07-06 21:09 ` Lucas De Marchi 2021-07-06 21:09 ` Lucas De Marchi 2021-07-07 8:34 ` Jani Nikula 2021-07-07 8:34 ` Jani Nikula 2021-07-07 15:40 ` Lucas De Marchi 2021-07-07 15:40 ` Lucas De Marchi 2021-07-06 20:57 ` Lucas De Marchi 2021-07-06 20:57 ` Lucas De Marchi 2021-07-01 20:23 ` [PATCH 02/53] drm/i915: Add XE_HP initial definitions Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 03/53] drm/i915: Fork DG1 interrupt handler Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-02 9:21 ` Daniel Vetter 2021-07-02 9:21 ` [Intel-gfx] " Daniel Vetter 2021-07-06 22:48 ` Lucas De Marchi 2021-07-06 22:48 ` Lucas De Marchi 2021-07-07 7:39 ` Daniel Vetter 2021-07-07 7:39 ` Daniel Vetter 2021-07-07 15:53 ` Lucas De Marchi 2021-07-07 15:53 ` Lucas De Marchi 2021-07-01 20:23 ` [PATCH 04/53] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 22:06 ` Lucas De Marchi 2021-07-01 22:06 ` [Intel-gfx] " Lucas De Marchi 2021-07-01 20:23 ` [PATCH 05/53] drm/i915/gen12: Use fuse info to enable SFC Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 22:19 ` Lucas De Marchi 2021-07-01 22:19 ` Lucas De Marchi 2021-07-02 12:08 ` Tvrtko Ursulin 2021-07-02 12:08 ` Tvrtko Ursulin 2021-07-01 20:23 ` [PATCH 06/53] drm/i915/selftests: Allow for larger engine counts Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 22:33 ` Lucas De Marchi 2021-07-01 22:33 ` [Intel-gfx] " Lucas De Marchi 2021-07-01 20:23 ` [PATCH 07/53] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-02 12:22 ` Tvrtko Ursulin 2021-07-02 12:22 ` Tvrtko Ursulin 2021-07-07 22:17 ` [Intel-gfx] [PATCH v2] " Matt Roper 2021-07-01 20:23 ` [PATCH 08/53] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-02 12:42 ` Tvrtko Ursulin 2021-07-02 12:42 ` Tvrtko Ursulin 2021-07-06 21:15 ` Lucas De Marchi 2021-07-06 21:15 ` Lucas De Marchi 2021-07-07 7:46 ` Tvrtko Ursulin 2021-07-07 7:46 ` Tvrtko Ursulin 2021-07-01 20:23 ` [PATCH 09/53] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 11/53] drm/i915/xehp: Define multicast register ranges Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 12/53] drm/i915/xehp: Handle new device context ID format Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 13/53] drm/i915/xehp: New engine context offsets Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 14/53] drm/i915/xehp: handle new steering options Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 15/53] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 16/53] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 21:41 ` Rodrigo Vivi 2021-07-01 21:41 ` [Intel-gfx] " Rodrigo Vivi 2021-07-02 7:57 ` Jani Nikula 2021-07-02 7:57 ` [Intel-gfx] " Jani Nikula 2021-07-07 22:20 ` [Intel-gfx] [PATCH v2] " Matt Roper 2021-07-01 20:23 ` [PATCH 17/53] drm/i915/xehp: Changes to ss/eu definitions Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 18/53] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 19/53] drm/i915/xehpsdv: Add compute DSS type Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 20/53] drm/i915/xehpsdv: Define steering tables Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 21/53] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 22/53] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 23/53] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 21:41 ` Rodrigo Vivi 2021-07-01 21:41 ` [Intel-gfx] " Rodrigo Vivi 2021-07-01 20:23 ` [PATCH 24/53] drm/i915/dg2: add DG2 platform info Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 25/53] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 26/53] drm/i915/dg2: Add forcewake table Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 27/53] drm/i915/dg2: Update LNCF steering ranges Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 28/53] drm/i915/dg2: Add SQIDI steering Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 29/53] drm/i915/dg2: Add new LRI reg offsets Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` Matt Roper [this message] 2021-07-01 20:24 ` [Intel-gfx] [PATCH 30/53] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper 2021-07-01 20:24 ` [PATCH 31/53] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 8:57 ` Lionel Landwerlin 2021-07-02 8:57 ` [Intel-gfx] " Lionel Landwerlin 2021-07-01 20:24 ` [PATCH 32/53] drm/i915/dg2: Define MOCS table for DG2 Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 33/53] drm/i915/dg2: Add fake PCH Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-06 21:47 ` Lucas De Marchi 2021-07-06 21:47 ` [Intel-gfx] " Lucas De Marchi 2021-07-01 20:24 ` [PATCH 34/53] drm/i915/dg2: Add cdclk table and reference clock Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 35/53] drm/i915/dg2: Skip shared DPLL handling Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 36/53] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 37/53] drm/i915/dg2: Setup display outputs Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 38/53] drm/i915/dg2: Add dbuf programming Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 39/53] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 40/53] drm/i915/dg2: Don't read DRAM info Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 41/53] drm/i915/dg2: DG2 has fixed memory bandwidth Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 42/53] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 43/53] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 44/53] drm/i915/dg2: Add vswing programming for SNPS phys Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 8:14 ` Jani Nikula 2021-07-02 8:14 ` [Intel-gfx] " Jani Nikula 2021-07-01 20:24 ` [PATCH 45/53] drm/i915/dg2: Update modeset sequences Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 8:16 ` Jani Nikula 2021-07-02 8:16 ` Jani Nikula 2021-07-07 22:22 ` [Intel-gfx] [PATCH v2] " Matt Roper 2021-07-09 18:25 ` Lucas De Marchi 2021-07-01 20:24 ` [PATCH 46/53] drm/i915/dg2: Classify DG2 PHY types Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 47/53] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 48/53] drm/i915/dg2: Update lane disable power state during PSR Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 49/53] drm/i915/dg2: Add DG2 to the PSR2 defeature list Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 50/53] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 8:19 ` Jani Nikula 2021-07-02 8:19 ` [Intel-gfx] " Jani Nikula 2021-08-23 5:42 ` Kulkarni, Vandita 2021-08-23 5:42 ` [Intel-gfx] " Kulkarni, Vandita 2021-07-01 20:24 ` [PATCH 51/53] drm/i915/display/dsc: Set BPP in the kernel Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 52/53] drm/i915/dg2: Update to bigjoiner path Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-09 0:11 ` Navare, Manasi 2021-07-09 0:11 ` [Intel-gfx] " Navare, Manasi 2021-07-01 20:24 ` [PATCH 53/53] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 1:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms Patchwork 2021-07-02 1:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-07-02 2:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-07-02 8:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-07-07 22:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Begin enabling Xe_HP SDV and DG2 platforms (rev4) Patchwork
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