From: jason-jh.lin <jason-jh.lin@mediatek.com>
To: <chunkuang.hu@kernel.org>, <matthias.bgg@gmail.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
<fshao@google.com>, <jason-jh.lin@mediatek.com>,
<nancy.lin@mediatek.com>, <singo.chang@mediatek.com>
Subject: [PATCH v3 07/12] arm64: dts: mt8195: add display node for vdosys0
Date: Fri, 16 Jul 2021 01:37:45 +0800 [thread overview]
Message-ID: <20210715173750.10852-8-jason-jh.lin@mediatek.com> (raw)
In-Reply-To: <20210715173750.10852-1-jason-jh.lin@mediatek.com>
Add display node for vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is based on [1][2][3]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2]arm64: dts: mt8195: add IOMMU and smi nodes
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3]arm64: dts: mt8195: add gce node
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@mediatek.com/
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 111 +++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 04d3e95175fa..aa2a7849b822 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1155,9 +1155,120 @@
#clock-cells = <1>;
};
+ ovl0: disp_ovl@1c000000 {
+ compatible = "mediatek,mt8195-disp-ovl",
+ "mediatek,mt8183-disp-ovl";
+ reg = <0 0x1c000000 0 0x1000>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>;
+ };
+
+ rdma0: disp_rdma@1c002000 {
+ compatible = "mediatek,mt8195-disp-rdma";
+ reg = <0 0x1c002000 0 0x1000>;
+ interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>;
+ };
+
+ color0: disp_color@1c003000 {
+ compatible = "mediatek,mt8195-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1c003000 0 0x1000>;
+ interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>;
+ };
+
+ ccorr0: disp_ccorr@1c004000 {
+ compatible = "mediatek,mt8195-disp-ccorr",
+ "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1c004000 0 0x1000>;
+ interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>;
+ };
+
+ aal0: disp_aal@1c005000 {
+ compatible = "mediatek,mt8195-disp-aal",
+ "mediatek,mt8173-disp-aal";
+ reg = <0 0x1c005000 0 0x1000>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>;
+ };
+
+ gamma0: disp_gamma@1c006000 {
+ compatible = "mediatek,mt8195-disp-gamma",
+ "mediatek,mt8173-disp-gamma";
+ reg = <0 0x1c006000 0 0x1000>;
+ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>;
+ };
+
+ dither0: disp_dither@1c007000 {
+ compatible = "mediatek,mt8195-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1c007000 0 0x1000>;
+ interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>;
+ };
+
+ dsc0: disp_dsc_wrap@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
+ merge0: disp_vpp_merge0@1c014000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c014000 0 0x1000>;
+ interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>;
+ };
+
+ mutex: disp_mutex0@1c016000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c016000 0 0x1000>;
+ reg-names = "vdo0_mutex";
+ interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+ clock-names = "vdo0_mutex";
+ mediatek,gce-events =
+ <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+ };
+
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-vdosys0", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
+ mboxes = <&gce1 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: jason-jh.lin <jason-jh.lin@mediatek.com>
To: <chunkuang.hu@kernel.org>, <matthias.bgg@gmail.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
<fshao@google.com>, <jason-jh.lin@mediatek.com>,
<nancy.lin@mediatek.com>, <singo.chang@mediatek.com>
Subject: [PATCH v3 07/12] arm64: dts: mt8195: add display node for vdosys0
Date: Fri, 16 Jul 2021 01:37:45 +0800 [thread overview]
Message-ID: <20210715173750.10852-8-jason-jh.lin@mediatek.com> (raw)
In-Reply-To: <20210715173750.10852-1-jason-jh.lin@mediatek.com>
Add display node for vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is based on [1][2][3]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2]arm64: dts: mt8195: add IOMMU and smi nodes
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3]arm64: dts: mt8195: add gce node
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@mediatek.com/
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 111 +++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 04d3e95175fa..aa2a7849b822 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1155,9 +1155,120 @@
#clock-cells = <1>;
};
+ ovl0: disp_ovl@1c000000 {
+ compatible = "mediatek,mt8195-disp-ovl",
+ "mediatek,mt8183-disp-ovl";
+ reg = <0 0x1c000000 0 0x1000>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>;
+ };
+
+ rdma0: disp_rdma@1c002000 {
+ compatible = "mediatek,mt8195-disp-rdma";
+ reg = <0 0x1c002000 0 0x1000>;
+ interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>;
+ };
+
+ color0: disp_color@1c003000 {
+ compatible = "mediatek,mt8195-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1c003000 0 0x1000>;
+ interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>;
+ };
+
+ ccorr0: disp_ccorr@1c004000 {
+ compatible = "mediatek,mt8195-disp-ccorr",
+ "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1c004000 0 0x1000>;
+ interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>;
+ };
+
+ aal0: disp_aal@1c005000 {
+ compatible = "mediatek,mt8195-disp-aal",
+ "mediatek,mt8173-disp-aal";
+ reg = <0 0x1c005000 0 0x1000>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>;
+ };
+
+ gamma0: disp_gamma@1c006000 {
+ compatible = "mediatek,mt8195-disp-gamma",
+ "mediatek,mt8173-disp-gamma";
+ reg = <0 0x1c006000 0 0x1000>;
+ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>;
+ };
+
+ dither0: disp_dither@1c007000 {
+ compatible = "mediatek,mt8195-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1c007000 0 0x1000>;
+ interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>;
+ };
+
+ dsc0: disp_dsc_wrap@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
+ merge0: disp_vpp_merge0@1c014000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c014000 0 0x1000>;
+ interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>;
+ };
+
+ mutex: disp_mutex0@1c016000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c016000 0 0x1000>;
+ reg-names = "vdo0_mutex";
+ interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+ clock-names = "vdo0_mutex";
+ mediatek,gce-events =
+ <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+ };
+
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-vdosys0", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
+ mboxes = <&gce1 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-07-15 17:49 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 01/12] dt-bindings: mediatek: display: change txt to yaml file jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin
2021-07-16 17:47 ` Rob Herring
2021-07-16 17:47 ` Rob Herring
2021-07-16 17:47 ` Rob Herring
2021-07-15 17:37 ` [PATCH v3 02/12] dt-bindings: mediatek: display: add definition for mt8195 jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin
2021-07-16 6:14 ` Fei Shao
2021-07-16 6:14 ` Fei Shao
2021-07-16 6:14 ` Fei Shao
2021-07-15 17:37 ` [PATCH v3 03/12] dt-bindings: mediatek: display: add MERGE additional description jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 04/12] dt-bindings: mediatek: add DSC definition for mt8195 jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 05/12] dt-bindings: arm: mediatek: change mmsys txt to yaml file jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin
2021-07-16 7:46 ` Fei Shao
2021-07-16 7:46 ` Fei Shao
2021-07-16 7:46 ` Fei Shao
2021-07-16 17:42 ` Rob Herring
2021-07-16 17:42 ` Rob Herring
2021-07-16 17:42 ` Rob Herring
2021-07-15 17:37 ` [PATCH v3 06/12] dt-bindings: arm: mediatek: add definition for mt8195 mmsys jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin [this message]
2021-07-15 17:37 ` [PATCH v3 07/12] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 08/12] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 09/12] soc: mediatek: add mtk-mutex " jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 10/12] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195 jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin
2021-07-16 4:35 ` CK Hu
2021-07-16 4:35 ` CK Hu
2021-07-15 17:37 ` [PATCH v3 11/12] drm/mediatek: add DSC " jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin
2021-07-15 23:21 ` Chun-Kuang Hu
2021-07-15 23:21 ` Chun-Kuang Hu
2021-07-15 23:21 ` Chun-Kuang Hu
2021-07-23 2:45 ` Jason-JH Lin
2021-07-23 2:45 ` Jason-JH Lin
2021-07-15 17:37 ` [PATCH v3 12/12] drm/mediatek: add MERGE " jason-jh.lin
2021-07-15 17:37 ` jason-jh.lin
2021-07-15 23:50 ` Chun-Kuang Hu
2021-07-15 23:50 ` Chun-Kuang Hu
2021-07-23 2:41 ` Jason-JH Lin
2021-07-23 2:41 ` Jason-JH Lin
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