From: Bjorn Helgaas <helgaas@kernel.org> To: Tim Harvey <tharvey@gateworks.com> Cc: "Richard Zhu" <hongxing.zhu@nxp.com>, "Lucas Stach" <l.stach@pengutronix.de>, "Bjorn Helgaas" <bhelgaas@google.com>, "Rob Herring" <robh+dt@kernel.org>, "Shawn Guo" <shawnguo@kernel.org>, "Sascha Hauer" <s.hauer@pengutronix.de>, "Pengutronix Kernel Team" <kernel@pengutronix.de>, "Fabio Estevam" <festevam@gmail.com>, "NXP Linux Team" <linux-imx@nxp.com>, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, "Krzysztof Wilczyński" <kw@linux.com>, "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com> Subject: Re: [PATCH 3/6] PCI: imx6: add IMX8MM support Date: Thu, 29 Jul 2021 17:29:17 -0500 [thread overview] Message-ID: <20210729222917.GA998237@bjorn-Precision-5520> (raw) In-Reply-To: <20210723204958.7186-4-tharvey@gateworks.com> Capitalize first letter of subject to match history: PCI: imx6: Add IMX8MM support On Fri, Jul 23, 2021 at 01:49:55PM -0700, Tim Harvey wrote: > Add IMX8MM support to the existing driver which shares most > functionality with the IMX8MM. > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> > --- > drivers/pci/controller/dwc/pci-imx6.c | 103 +++++++++++++++++++++++++- > 1 file changed, 102 insertions(+), 1 deletion(-) > + case IMX8MM: > + offset = imx6_pcie_grp_offset(imx6_pcie); > + > + dev_info(imx6_pcie->pci->dev, "%s REF_CLK is used!.\n", > + imx6_pcie->ext_osc ? "EXT" : "PLL"); > + if (imx6_pcie->ext_osc) { > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MQ_GPR_PCIE_REF_USE_PAD, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_SEL); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_AUX_EN, > + IMX8MM_GPR_PCIE_AUX_EN); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_POWER_OFF, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_SSC_EN, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_EXT); > + udelay(100); > + /* Do the PHY common block reset */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_CMN_RST, > + IMX8MM_GPR_PCIE_CMN_RST); > + udelay(200); > + } else { > + /* Configure the internal PLL as REF clock */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MQ_GPR_PCIE_REF_USE_PAD, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_SEL); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_AUX_EN, > + IMX8MM_GPR_PCIE_AUX_EN); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_POWER_OFF, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_SSC_EN, 0); Seems like all the above is common to both cases? If so, it's a shame to repeat it because it makes it hard to see what's different. > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_PLL); > + udelay(100); > + /* Configure the PHY */ > + writel(PCIE_PHY_CMN_REG62_PLL_CLK_OUT, > + imx6_pcie->phy_base + PCIE_PHY_CMN_REG62); > + writel(PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM, > + imx6_pcie->phy_base + PCIE_PHY_CMN_REG64); > + /* Do the PHY common block reset */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_CMN_RST, > + IMX8MM_GPR_PCIE_CMN_RST); > + udelay(200); > + } > + /* > + * In order to pass the compliance tests. > + * Configure the TRSV regiser of iMX8MM PCIe PHY. The "In order to ..." line isn't quite a sentence. Maybe it should be joined with the second line? s/regiser/register/ ? > + */ > + writel(PCIE_PHY_TRSV_REG5_GEN1_DEEMP, > + imx6_pcie->phy_base + PCIE_PHY_TRSV_REG5); > + /* check for EXT osc */ Since you have a comment here, it would be useful to spell out "osc" for newbies like me. I assume it's short for "oscillator"? > + imx6_pcie->ext_osc = of_property_read_bool(node, "fsl,ext-osc");
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org> To: Tim Harvey <tharvey@gateworks.com> Cc: "Richard Zhu" <hongxing.zhu@nxp.com>, "Lucas Stach" <l.stach@pengutronix.de>, "Bjorn Helgaas" <bhelgaas@google.com>, "Rob Herring" <robh+dt@kernel.org>, "Shawn Guo" <shawnguo@kernel.org>, "Sascha Hauer" <s.hauer@pengutronix.de>, "Pengutronix Kernel Team" <kernel@pengutronix.de>, "Fabio Estevam" <festevam@gmail.com>, "NXP Linux Team" <linux-imx@nxp.com>, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, "Krzysztof Wilczyński" <kw@linux.com>, "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com> Subject: Re: [PATCH 3/6] PCI: imx6: add IMX8MM support Date: Thu, 29 Jul 2021 17:29:17 -0500 [thread overview] Message-ID: <20210729222917.GA998237@bjorn-Precision-5520> (raw) In-Reply-To: <20210723204958.7186-4-tharvey@gateworks.com> Capitalize first letter of subject to match history: PCI: imx6: Add IMX8MM support On Fri, Jul 23, 2021 at 01:49:55PM -0700, Tim Harvey wrote: > Add IMX8MM support to the existing driver which shares most > functionality with the IMX8MM. > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> > --- > drivers/pci/controller/dwc/pci-imx6.c | 103 +++++++++++++++++++++++++- > 1 file changed, 102 insertions(+), 1 deletion(-) > + case IMX8MM: > + offset = imx6_pcie_grp_offset(imx6_pcie); > + > + dev_info(imx6_pcie->pci->dev, "%s REF_CLK is used!.\n", > + imx6_pcie->ext_osc ? "EXT" : "PLL"); > + if (imx6_pcie->ext_osc) { > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MQ_GPR_PCIE_REF_USE_PAD, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_SEL); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_AUX_EN, > + IMX8MM_GPR_PCIE_AUX_EN); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_POWER_OFF, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_SSC_EN, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_EXT); > + udelay(100); > + /* Do the PHY common block reset */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_CMN_RST, > + IMX8MM_GPR_PCIE_CMN_RST); > + udelay(200); > + } else { > + /* Configure the internal PLL as REF clock */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MQ_GPR_PCIE_REF_USE_PAD, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_SEL); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_AUX_EN, > + IMX8MM_GPR_PCIE_AUX_EN); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_POWER_OFF, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_SSC_EN, 0); Seems like all the above is common to both cases? If so, it's a shame to repeat it because it makes it hard to see what's different. > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_PLL); > + udelay(100); > + /* Configure the PHY */ > + writel(PCIE_PHY_CMN_REG62_PLL_CLK_OUT, > + imx6_pcie->phy_base + PCIE_PHY_CMN_REG62); > + writel(PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM, > + imx6_pcie->phy_base + PCIE_PHY_CMN_REG64); > + /* Do the PHY common block reset */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_CMN_RST, > + IMX8MM_GPR_PCIE_CMN_RST); > + udelay(200); > + } > + /* > + * In order to pass the compliance tests. > + * Configure the TRSV regiser of iMX8MM PCIe PHY. The "In order to ..." line isn't quite a sentence. Maybe it should be joined with the second line? s/regiser/register/ ? > + */ > + writel(PCIE_PHY_TRSV_REG5_GEN1_DEEMP, > + imx6_pcie->phy_base + PCIE_PHY_TRSV_REG5); > + /* check for EXT osc */ Since you have a comment here, it would be useful to spell out "osc" for newbies like me. I assume it's short for "oscillator"? > + imx6_pcie->ext_osc = of_property_read_bool(node, "fsl,ext-osc"); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-07-29 22:29 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-23 20:49 [PATCH 0/6] Add IMX8M Mini PCI support Tim Harvey 2021-07-23 20:49 ` Tim Harvey 2021-07-23 20:49 ` [PATCH 1/6] dt-bindings: imx6q-pcie: add compatible for IMX8MM support Tim Harvey 2021-07-23 20:49 ` Tim Harvey 2021-07-23 20:49 ` [PATCH 2/6] dt-bindings: reset: imx8mq: add pcie reset Tim Harvey 2021-07-23 20:49 ` Tim Harvey 2021-07-23 20:49 ` [PATCH 3/6] PCI: imx6: add IMX8MM support Tim Harvey 2021-07-23 20:49 ` Tim Harvey 2021-07-29 22:29 ` Bjorn Helgaas [this message] 2021-07-29 22:29 ` Bjorn Helgaas 2021-07-23 20:49 ` [PATCH 4/6] reset: imx7: add resets for PCIe Tim Harvey 2021-07-23 20:49 ` Tim Harvey 2021-07-23 20:49 ` [PATCH 5/6] arm64: dts: imx8mm: add PCIe support Tim Harvey 2021-07-23 20:49 ` Tim Harvey 2021-07-29 14:25 ` Rob Herring 2021-07-29 14:25 ` Rob Herring 2021-07-23 20:49 ` [PATCH 6/6] arm64: dts: imx8mm: add gpc iomux compatible Tim Harvey 2021-07-23 20:49 ` Tim Harvey 2021-07-29 14:39 ` [PATCH 0/6] Add IMX8M Mini PCI support Ahmad Fatoum 2021-07-29 14:39 ` Ahmad Fatoum 2021-07-30 1:27 ` Richard Zhu 2021-07-30 1:27 ` Richard Zhu 2021-08-16 15:39 ` Tim Harvey 2021-08-16 15:39 ` Tim Harvey 2021-10-11 12:25 ` Adam Ford 2021-10-11 12:25 ` Adam Ford 2021-10-11 12:30 ` Lucas Stach 2021-10-11 12:30 ` Lucas Stach 2021-10-11 12:31 ` Adam Ford 2021-10-11 12:31 ` Adam Ford 2021-10-11 15:29 ` Tim Harvey 2021-10-11 15:29 ` Tim Harvey 2021-10-12 8:29 ` Richard Zhu 2021-10-12 8:29 ` Richard Zhu
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