From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [RFC PATCH 06/13] target/riscv: Fix div instructions Date: Thu, 5 Aug 2021 10:53:05 +0800 [thread overview] Message-ID: <20210805025312.15720-7-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Don't overwrite global source register after https://lists.gnu.org/archive/html/qemu-riscv/2021-07/msg00058.html. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/translate.c | 46 +++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 20 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 912e5f1061..2892eaa9a7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -265,7 +265,7 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) static void gen_div(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, cond2, zeroreg, resultopt1; + TCGv cond1, cond2, zeroreg, resultopt1, t1, t2; /* * Handle by altering args to tcg_gen_div to produce req'd results: * For overflow: want source1 in source1 and 1 in source2 @@ -275,6 +275,8 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2) cond2 = tcg_temp_new(); zeroreg = tcg_constant_tl(0); resultopt1 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); tcg_gen_movi_tl(resultopt1, (target_ulong)-1); tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); @@ -283,49 +285,52 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2) tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ /* if div by zero, set source1 to -1, otherwise don't change */ - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, - resultopt1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, cond2, zeroreg, source1, resultopt1); /* if overflow or div by zero, set source2 to 1, else don't change */ tcg_gen_or_tl(cond1, cond1, cond2); tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_div_tl(ret, source1, source2); + tcg_gen_movcond_tl(TCG_COND_EQ, t2, cond1, zeroreg, source2, resultopt1); + tcg_gen_div_tl(ret, t1, t2); tcg_temp_free(cond1); tcg_temp_free(cond2); tcg_temp_free(resultopt1); + tcg_temp_free(t1); + tcg_temp_free(t2); } static void gen_divu(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, zeroreg, resultopt1; + TCGv cond1, zeroreg, resultopt1, t1, t2; cond1 = tcg_temp_new(); zeroreg = tcg_constant_tl(0); resultopt1 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); tcg_gen_movi_tl(resultopt1, (target_ulong)-1); - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, - resultopt1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, cond1, zeroreg, source1, resultopt1); tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_divu_tl(ret, source1, source2); + tcg_gen_movcond_tl(TCG_COND_EQ, t2, cond1, zeroreg, source2, resultopt1); + tcg_gen_divu_tl(ret, t1, t2); tcg_temp_free(cond1); tcg_temp_free(resultopt1); + tcg_temp_free(t1); + tcg_temp_free(t2); } static void gen_rem(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, cond2, zeroreg, resultopt1; + TCGv cond1, cond2, zeroreg, resultopt1, t2; cond1 = tcg_temp_new(); cond2 = tcg_temp_new(); zeroreg = tcg_constant_tl(0); resultopt1 = tcg_temp_new(); + t2 = tcg_temp_new(); tcg_gen_movi_tl(resultopt1, 1L); tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); @@ -335,9 +340,8 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2) tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ /* if overflow or div by zero, set source2 to 1, else don't change */ tcg_gen_or_tl(cond2, cond1, cond2); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, - resultopt1); - tcg_gen_rem_tl(resultopt1, source1, source2); + tcg_gen_movcond_tl(TCG_COND_EQ, t2, cond2, zeroreg, source2, resultopt1); + tcg_gen_rem_tl(resultopt1, source1, t2); /* if div by zero, just return the original dividend */ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, source1); @@ -345,26 +349,28 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2) tcg_temp_free(cond1); tcg_temp_free(cond2); tcg_temp_free(resultopt1); + tcg_temp_free(t2); } static void gen_remu(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, zeroreg, resultopt1; + TCGv cond1, zeroreg, resultopt1, t2; cond1 = tcg_temp_new(); zeroreg = tcg_constant_tl(0); resultopt1 = tcg_temp_new(); + t2 = tcg_temp_new(); tcg_gen_movi_tl(resultopt1, (target_ulong)1); tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_remu_tl(resultopt1, source1, source2); + tcg_gen_movcond_tl(TCG_COND_EQ, t2, cond1, zeroreg, source2, resultopt1); + tcg_gen_remu_tl(resultopt1, source1, t2); /* if div by zero, just return the original dividend */ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, source1); tcg_temp_free(cond1); tcg_temp_free(resultopt1); + tcg_temp_free(t2); } static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [RFC PATCH 06/13] target/riscv: Fix div instructions Date: Thu, 5 Aug 2021 10:53:05 +0800 [thread overview] Message-ID: <20210805025312.15720-7-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Don't overwrite global source register after https://lists.gnu.org/archive/html/qemu-riscv/2021-07/msg00058.html. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/translate.c | 46 +++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 20 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 912e5f1061..2892eaa9a7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -265,7 +265,7 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) static void gen_div(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, cond2, zeroreg, resultopt1; + TCGv cond1, cond2, zeroreg, resultopt1, t1, t2; /* * Handle by altering args to tcg_gen_div to produce req'd results: * For overflow: want source1 in source1 and 1 in source2 @@ -275,6 +275,8 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2) cond2 = tcg_temp_new(); zeroreg = tcg_constant_tl(0); resultopt1 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); tcg_gen_movi_tl(resultopt1, (target_ulong)-1); tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); @@ -283,49 +285,52 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2) tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ /* if div by zero, set source1 to -1, otherwise don't change */ - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, - resultopt1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, cond2, zeroreg, source1, resultopt1); /* if overflow or div by zero, set source2 to 1, else don't change */ tcg_gen_or_tl(cond1, cond1, cond2); tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_div_tl(ret, source1, source2); + tcg_gen_movcond_tl(TCG_COND_EQ, t2, cond1, zeroreg, source2, resultopt1); + tcg_gen_div_tl(ret, t1, t2); tcg_temp_free(cond1); tcg_temp_free(cond2); tcg_temp_free(resultopt1); + tcg_temp_free(t1); + tcg_temp_free(t2); } static void gen_divu(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, zeroreg, resultopt1; + TCGv cond1, zeroreg, resultopt1, t1, t2; cond1 = tcg_temp_new(); zeroreg = tcg_constant_tl(0); resultopt1 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); tcg_gen_movi_tl(resultopt1, (target_ulong)-1); - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, - resultopt1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, cond1, zeroreg, source1, resultopt1); tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_divu_tl(ret, source1, source2); + tcg_gen_movcond_tl(TCG_COND_EQ, t2, cond1, zeroreg, source2, resultopt1); + tcg_gen_divu_tl(ret, t1, t2); tcg_temp_free(cond1); tcg_temp_free(resultopt1); + tcg_temp_free(t1); + tcg_temp_free(t2); } static void gen_rem(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, cond2, zeroreg, resultopt1; + TCGv cond1, cond2, zeroreg, resultopt1, t2; cond1 = tcg_temp_new(); cond2 = tcg_temp_new(); zeroreg = tcg_constant_tl(0); resultopt1 = tcg_temp_new(); + t2 = tcg_temp_new(); tcg_gen_movi_tl(resultopt1, 1L); tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); @@ -335,9 +340,8 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2) tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ /* if overflow or div by zero, set source2 to 1, else don't change */ tcg_gen_or_tl(cond2, cond1, cond2); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, - resultopt1); - tcg_gen_rem_tl(resultopt1, source1, source2); + tcg_gen_movcond_tl(TCG_COND_EQ, t2, cond2, zeroreg, source2, resultopt1); + tcg_gen_rem_tl(resultopt1, source1, t2); /* if div by zero, just return the original dividend */ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, source1); @@ -345,26 +349,28 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2) tcg_temp_free(cond1); tcg_temp_free(cond2); tcg_temp_free(resultopt1); + tcg_temp_free(t2); } static void gen_remu(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, zeroreg, resultopt1; + TCGv cond1, zeroreg, resultopt1, t2; cond1 = tcg_temp_new(); zeroreg = tcg_constant_tl(0); resultopt1 = tcg_temp_new(); + t2 = tcg_temp_new(); tcg_gen_movi_tl(resultopt1, (target_ulong)1); tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_remu_tl(resultopt1, source1, source2); + tcg_gen_movcond_tl(TCG_COND_EQ, t2, cond1, zeroreg, source2, resultopt1); + tcg_gen_remu_tl(resultopt1, source1, t2); /* if div by zero, just return the original dividend */ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, source1); tcg_temp_free(cond1); tcg_temp_free(resultopt1); + tcg_temp_free(t2); } static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) -- 2.17.1
next prev parent reply other threads:[~2021-08-05 2:59 UTC|newest] Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-05 2:52 [RFC PATCH 00/13] Support UXL field in mstatus LIU Zhiwei 2021-08-05 2:52 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 01/13] target/riscv: Add UXL to tb flags LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 6:00 ` Alistair Francis 2021-08-05 6:00 ` Alistair Francis 2021-08-05 19:01 ` Richard Henderson 2021-08-05 19:01 ` Richard Henderson 2021-08-06 2:49 ` LIU Zhiwei 2021-08-06 2:49 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 19:06 ` Richard Henderson 2021-08-05 19:06 ` Richard Henderson 2021-08-09 1:45 ` LIU Zhiwei 2021-08-09 1:45 ` LIU Zhiwei 2021-08-09 19:34 ` Richard Henderson 2021-08-09 19:34 ` Richard Henderson 2021-08-11 14:57 ` LIU Zhiwei 2021-08-11 14:57 ` LIU Zhiwei 2021-08-11 17:56 ` Richard Henderson 2021-08-11 17:56 ` Richard Henderson 2021-08-11 22:40 ` LIU Zhiwei 2021-08-11 22:40 ` LIU Zhiwei 2021-08-12 4:42 ` Richard Henderson 2021-08-12 4:42 ` Richard Henderson 2021-08-12 5:03 ` LIU Zhiwei 2021-08-12 5:03 ` LIU Zhiwei 2021-08-12 6:12 ` Richard Henderson 2021-08-12 6:12 ` Richard Henderson 2021-08-12 7:20 ` LIU Zhiwei 2021-08-12 7:20 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 03/13] target/riscv: Support UXL32 on 64-bit cpu for load/store LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 19:08 ` Richard Henderson 2021-08-05 19:08 ` Richard Henderson 2021-08-09 1:50 ` LIU Zhiwei 2021-08-09 1:50 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 04/13] target/riscv: Support UXL32 for slit/sltiu LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 19:09 ` Richard Henderson 2021-08-05 19:09 ` Richard Henderson 2021-08-09 7:28 ` LIU Zhiwei 2021-08-09 7:28 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 22:17 ` Richard Henderson 2021-08-05 22:17 ` Richard Henderson 2021-08-09 7:51 ` LIU Zhiwei 2021-08-09 7:51 ` LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei [this message] 2021-08-05 2:53 ` [RFC PATCH 06/13] target/riscv: Fix div instructions LIU Zhiwei 2021-08-05 22:18 ` Richard Henderson 2021-08-05 22:18 ` Richard Henderson 2021-08-09 7:53 ` LIU Zhiwei 2021-08-09 7:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 07/13] target/riscv: Support UXL32 for RVM LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 08/13] target/riscv: Support UXL32 for vector instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 09/13] target/riscv: Support UXL32 for atomic instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 11/13] target/riscv: Fix srow LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 13/13] target/riscv: Changing the width of U-mode CSR LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 6:01 ` [RFC PATCH 00/13] Support UXL field in mstatus Alistair Francis 2021-08-05 6:01 ` Alistair Francis 2021-08-05 7:14 ` LIU Zhiwei 2021-08-05 7:14 ` LIU Zhiwei 2021-08-05 7:20 ` Bin Meng 2021-08-05 7:20 ` Bin Meng 2021-08-05 8:10 ` LIU Zhiwei 2021-08-05 8:10 ` LIU Zhiwei 2021-08-06 10:05 ` Alistair Francis 2021-08-06 10:05 ` Alistair Francis 2021-08-09 1:25 ` LIU Zhiwei 2021-08-09 1:25 ` LIU Zhiwei
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