From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: Alistair.Francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Subject: [PATCH v2 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Date: Tue, 17 Aug 2021 11:17:59 -1000 [thread overview] Message-ID: <20210817211803.283639-18-richard.henderson@linaro.org> (raw) In-Reply-To: <20210817211803.283639-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn_trans/trans_rvb.c.inc | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index af7694ed29..d5a036b1f3 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -647,21 +647,18 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a) return gen_arith(ctx, a, EXT_NONE, gen_add_uw); } +static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt) +{ + if (shamt < 32) { + tcg_gen_deposit_z_tl(dest, src, shamt, 32); + } else { + tcg_gen_shli_tl(dest, src, shamt); + } +} + static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - - TCGv source1 = tcg_temp_new(); - gen_get_gpr(ctx, source1, a->rs1); - - if (a->shamt < 32) { - tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32); - } else { - tcg_gen_shli_tl(source1, source1, a->shamt); - } - - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - return true; + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw); } -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com, Alistair.Francis@wdc.com, bin.meng@windriver.com Subject: [PATCH v2 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Date: Tue, 17 Aug 2021 11:17:59 -1000 [thread overview] Message-ID: <20210817211803.283639-18-richard.henderson@linaro.org> (raw) In-Reply-To: <20210817211803.283639-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn_trans/trans_rvb.c.inc | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index af7694ed29..d5a036b1f3 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -647,21 +647,18 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a) return gen_arith(ctx, a, EXT_NONE, gen_add_uw); } +static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt) +{ + if (shamt < 32) { + tcg_gen_deposit_z_tl(dest, src, shamt, 32); + } else { + tcg_gen_shli_tl(dest, src, shamt); + } +} + static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - - TCGv source1 = tcg_temp_new(); - gen_get_gpr(ctx, source1, a->rs1); - - if (a->shamt < 32) { - tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32); - } else { - tcg_gen_shli_tl(source1, source1, a->shamt); - } - - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - return true; + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw); } -- 2.25.1
next prev parent reply other threads:[~2021-08-17 21:29 UTC|newest] Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-17 21:17 [PATCH v2 00/21] target/riscv: Use tcg_constant_* Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-17 21:17 ` [PATCH v2 01/21] " Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-18 7:23 ` Bin Meng 2021-08-18 7:23 ` Bin Meng 2021-08-17 21:17 ` [PATCH v2 02/21] target/riscv: Clean up division helpers Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-18 9:20 ` Bin Meng 2021-08-18 9:20 ` Bin Meng 2021-08-17 21:17 ` [PATCH v2 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-17 22:15 ` Philippe Mathieu-Daudé 2021-08-17 22:15 ` Philippe Mathieu-Daudé 2021-08-18 9:27 ` Bin Meng 2021-08-18 9:27 ` Bin Meng 2021-08-19 6:20 ` Alistair Francis 2021-08-19 6:20 ` Alistair Francis 2021-08-17 21:17 ` [PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-18 10:58 ` Bin Meng 2021-08-18 10:58 ` Bin Meng 2021-08-19 1:16 ` Richard Henderson 2021-08-19 1:16 ` Richard Henderson 2021-08-19 2:01 ` Richard Henderson 2021-08-19 2:01 ` Richard Henderson 2021-08-19 6:25 ` Alistair Francis 2021-08-19 6:25 ` Alistair Francis 2021-08-17 21:17 ` [PATCH v2 05/21] target/riscv: Add DisasExtend to gen_arith* Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-19 2:42 ` Bin Meng 2021-08-19 2:42 ` Bin Meng 2021-08-19 6:28 ` Alistair Francis 2021-08-19 6:28 ` Alistair Francis 2021-08-17 21:17 ` [PATCH v2 06/21] target/riscv: Remove gen_arith_div* Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-19 2:43 ` Bin Meng 2021-08-19 2:43 ` Bin Meng 2021-08-19 6:28 ` Alistair Francis 2021-08-19 6:28 ` Alistair Francis 2021-08-17 21:17 ` [PATCH v2 07/21] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-19 3:03 ` Bin Meng 2021-08-19 3:03 ` Bin Meng 2021-08-19 6:29 ` Alistair Francis 2021-08-19 6:29 ` Alistair Francis 2021-08-17 21:17 ` [PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-17 22:19 ` Philippe Mathieu-Daudé 2021-08-17 22:19 ` Philippe Mathieu-Daudé 2021-08-19 3:03 ` Bin Meng 2021-08-19 3:03 ` Bin Meng 2021-08-17 21:17 ` [PATCH v2 09/21] target/riscv: Move gen_* helpers for RVB Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-17 22:20 ` Philippe Mathieu-Daudé 2021-08-17 22:20 ` Philippe Mathieu-Daudé 2021-08-19 3:03 ` Bin Meng 2021-08-19 3:03 ` Bin Meng 2021-08-17 21:17 ` [PATCH v2 10/21] target/riscv: Add DisasExtend to gen_unary Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-17 21:17 ` [PATCH v2 11/21] target/riscv: Use DisasExtend in shift operations Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-19 6:13 ` Bin Meng 2021-08-19 6:13 ` Bin Meng 2021-08-17 21:17 ` [PATCH v2 12/21] target/riscv: Add gen_greviw Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-17 21:17 ` [PATCH v2 13/21] target/riscv: Use get_gpr in branches Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-19 6:19 ` Bin Meng 2021-08-19 6:19 ` Bin Meng 2021-08-17 21:17 ` [PATCH v2 14/21] target/riscv: Use {get, dest}_gpr for integer load/store Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-19 6:22 ` Bin Meng 2021-08-19 6:22 ` Bin Meng 2021-08-17 21:17 ` [PATCH v2 15/21] target/riscv: Reorg csr instructions Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-19 7:08 ` Bin Meng 2021-08-19 7:08 ` Bin Meng 2021-08-17 21:17 ` [PATCH v2 16/21] target/riscv: Use {get,dest}_gpr for RVA Richard Henderson 2021-08-17 21:17 ` Richard Henderson 2021-08-19 8:04 ` Bin Meng 2021-08-19 8:04 ` Bin Meng 2021-08-17 21:17 ` Richard Henderson [this message] 2021-08-17 21:17 ` [PATCH v2 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Richard Henderson 2021-08-17 21:18 ` [PATCH v2 18/21] target/riscv: Use {get,dest}_gpr for RVF Richard Henderson 2021-08-17 21:18 ` Richard Henderson 2021-08-19 8:04 ` Bin Meng 2021-08-19 8:04 ` Bin Meng 2021-08-17 21:18 ` [PATCH v2 19/21] target/riscv: Use {get,dest}_gpr for RVD Richard Henderson 2021-08-17 21:18 ` Richard Henderson 2021-08-19 8:04 ` Bin Meng 2021-08-19 8:04 ` Bin Meng 2021-08-17 21:18 ` [PATCH v2 20/21] target/riscv: Tidy trans_rvh.c.inc Richard Henderson 2021-08-17 21:18 ` Richard Henderson 2021-08-17 22:24 ` Philippe Mathieu-Daudé 2021-08-17 22:24 ` Philippe Mathieu-Daudé 2021-08-17 21:18 ` [PATCH v2 21/21] target/riscv: Use {get,dest}_gpr for RVV Richard Henderson 2021-08-17 21:18 ` Richard Henderson
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