From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: <daniel.vetter@ffwll.ch>, <tony.ye@intel.com>, <zhengguo.xu@intel.com> Subject: [PATCH 10/27] drm/i915/guc: Introduce context parent-child relationship Date: Fri, 20 Aug 2021 15:44:29 -0700 [thread overview] Message-ID: <20210820224446.30620-11-matthew.brost@intel.com> (raw) In-Reply-To: <20210820224446.30620-1-matthew.brost@intel.com> Introduce context parent-child relationship. Once this relationship is created all pinning / unpinning operations are directed to the parent context. The parent context is responsible for pinning all of its' children and itself. This is a precursor to the full GuC multi-lrc implementation but aligns to how GuC mutli-lrc interface is defined - a single H2G is used register / deregister all of the contexts simultaneously. Subsequent patches in the series will implement the pinning / unpinning operations for parent / child contexts. v2: (Daniel Vetter) - Add kernel doc, add wrapper to access parent to ensure safety Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/gt/intel_context.c | 29 ++++++++++++++ drivers/gpu/drm/i915/gt/intel_context.h | 39 +++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_context_types.h | 23 +++++++++++ 3 files changed, 91 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index 508cfe5770c0..00d1aee6d199 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -404,6 +404,8 @@ intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine) INIT_LIST_HEAD(&ce->destroyed_link); + INIT_LIST_HEAD(&ce->guc_child_list); + /* * Initialize fence to be complete as this is expected to be complete * unless there is a pending schedule disable outstanding. @@ -418,10 +420,17 @@ intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine) void intel_context_fini(struct intel_context *ce) { + struct intel_context *child, *next; + if (ce->timeline) intel_timeline_put(ce->timeline); i915_vm_put(ce->vm); + /* Need to put the creation ref for the children */ + if (intel_context_is_parent(ce)) + for_each_child_safe(ce, child, next) + intel_context_put(child); + mutex_destroy(&ce->pin_mutex); i915_active_fini(&ce->active); } @@ -537,6 +546,26 @@ struct i915_request *intel_context_find_active_request(struct intel_context *ce) return active; } +void intel_context_bind_parent_child(struct intel_context *parent, + struct intel_context *child) +{ + /* + * Callers responsibility to validate that this function is used + * correctly but we use GEM_BUG_ON here ensure that they do. + */ + GEM_BUG_ON(!intel_engine_uses_guc(parent->engine)); + GEM_BUG_ON(intel_context_is_pinned(parent)); + GEM_BUG_ON(intel_context_is_child(parent)); + GEM_BUG_ON(intel_context_is_pinned(child)); + GEM_BUG_ON(intel_context_is_child(child)); + GEM_BUG_ON(intel_context_is_parent(child)); + + parent->guc_number_children++; + list_add_tail(&child->guc_child_link, + &parent->guc_child_list); + child->parent = parent; +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftest_context.c" #endif diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h index c41098950746..c2985822ab74 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.h +++ b/drivers/gpu/drm/i915/gt/intel_context.h @@ -44,6 +44,45 @@ void intel_context_free(struct intel_context *ce); int intel_context_reconfigure_sseu(struct intel_context *ce, const struct intel_sseu sseu); +static inline bool intel_context_is_child(struct intel_context *ce) +{ + return !!ce->parent; +} + +static inline bool intel_context_is_parent(struct intel_context *ce) +{ + return !!ce->guc_number_children; +} + +static inline bool intel_context_is_pinned(struct intel_context *ce); + +static inline struct intel_context * +intel_context_to_parent(struct intel_context *ce) +{ + if (intel_context_is_child(ce)) { + /* + * The parent holds ref count to the child so it is always safe + * for the parent to access the child, but the child has pointer + * to the parent without a ref. To ensure this is safe the child + * should only access the parent pointer while the parent is + * pinned. + */ + GEM_BUG_ON(!intel_context_is_pinned(ce->parent)); + + return ce->parent; + } else { + return ce; + } +} + +void intel_context_bind_parent_child(struct intel_context *parent, + struct intel_context *child); + +#define for_each_child(parent, ce)\ + list_for_each_entry(ce, &(parent)->guc_child_list, guc_child_link) +#define for_each_child_safe(parent, ce, cn)\ + list_for_each_entry_safe(ce, cn, &(parent)->guc_child_list, guc_child_link) + /** * intel_context_lock_pinned - Stablises the 'pinned' status of the HW context * @ce - the context diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index fd338a30617e..0fafc178cf2c 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -213,6 +213,29 @@ struct intel_context { */ struct list_head destroyed_link; + /** anonymous struct for parent / children only members */ + struct { + union { + /** + * @guc_child_list: parent's list of of children + * contexts, no protection as immutable after context + * creation + */ + struct list_head guc_child_list; + /** + * @guc_child_link: child's link into parent's list of + * children + */ + struct list_head guc_child_link; + }; + + /** @parent: pointer to parent if child */ + struct intel_context *parent; + + /** @guc_number_children: number of children if parent */ + u8 guc_number_children; + }; + #ifdef CONFIG_DRM_I915_SELFTEST /** * @drop_schedule_enable: Force drop of schedule enable G2H for selftest -- 2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: <daniel.vetter@ffwll.ch>, <tony.ye@intel.com>, <zhengguo.xu@intel.com> Subject: [Intel-gfx] [PATCH 10/27] drm/i915/guc: Introduce context parent-child relationship Date: Fri, 20 Aug 2021 15:44:29 -0700 [thread overview] Message-ID: <20210820224446.30620-11-matthew.brost@intel.com> (raw) In-Reply-To: <20210820224446.30620-1-matthew.brost@intel.com> Introduce context parent-child relationship. Once this relationship is created all pinning / unpinning operations are directed to the parent context. The parent context is responsible for pinning all of its' children and itself. This is a precursor to the full GuC multi-lrc implementation but aligns to how GuC mutli-lrc interface is defined - a single H2G is used register / deregister all of the contexts simultaneously. Subsequent patches in the series will implement the pinning / unpinning operations for parent / child contexts. v2: (Daniel Vetter) - Add kernel doc, add wrapper to access parent to ensure safety Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/gt/intel_context.c | 29 ++++++++++++++ drivers/gpu/drm/i915/gt/intel_context.h | 39 +++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_context_types.h | 23 +++++++++++ 3 files changed, 91 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index 508cfe5770c0..00d1aee6d199 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -404,6 +404,8 @@ intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine) INIT_LIST_HEAD(&ce->destroyed_link); + INIT_LIST_HEAD(&ce->guc_child_list); + /* * Initialize fence to be complete as this is expected to be complete * unless there is a pending schedule disable outstanding. @@ -418,10 +420,17 @@ intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine) void intel_context_fini(struct intel_context *ce) { + struct intel_context *child, *next; + if (ce->timeline) intel_timeline_put(ce->timeline); i915_vm_put(ce->vm); + /* Need to put the creation ref for the children */ + if (intel_context_is_parent(ce)) + for_each_child_safe(ce, child, next) + intel_context_put(child); + mutex_destroy(&ce->pin_mutex); i915_active_fini(&ce->active); } @@ -537,6 +546,26 @@ struct i915_request *intel_context_find_active_request(struct intel_context *ce) return active; } +void intel_context_bind_parent_child(struct intel_context *parent, + struct intel_context *child) +{ + /* + * Callers responsibility to validate that this function is used + * correctly but we use GEM_BUG_ON here ensure that they do. + */ + GEM_BUG_ON(!intel_engine_uses_guc(parent->engine)); + GEM_BUG_ON(intel_context_is_pinned(parent)); + GEM_BUG_ON(intel_context_is_child(parent)); + GEM_BUG_ON(intel_context_is_pinned(child)); + GEM_BUG_ON(intel_context_is_child(child)); + GEM_BUG_ON(intel_context_is_parent(child)); + + parent->guc_number_children++; + list_add_tail(&child->guc_child_link, + &parent->guc_child_list); + child->parent = parent; +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftest_context.c" #endif diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h index c41098950746..c2985822ab74 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.h +++ b/drivers/gpu/drm/i915/gt/intel_context.h @@ -44,6 +44,45 @@ void intel_context_free(struct intel_context *ce); int intel_context_reconfigure_sseu(struct intel_context *ce, const struct intel_sseu sseu); +static inline bool intel_context_is_child(struct intel_context *ce) +{ + return !!ce->parent; +} + +static inline bool intel_context_is_parent(struct intel_context *ce) +{ + return !!ce->guc_number_children; +} + +static inline bool intel_context_is_pinned(struct intel_context *ce); + +static inline struct intel_context * +intel_context_to_parent(struct intel_context *ce) +{ + if (intel_context_is_child(ce)) { + /* + * The parent holds ref count to the child so it is always safe + * for the parent to access the child, but the child has pointer + * to the parent without a ref. To ensure this is safe the child + * should only access the parent pointer while the parent is + * pinned. + */ + GEM_BUG_ON(!intel_context_is_pinned(ce->parent)); + + return ce->parent; + } else { + return ce; + } +} + +void intel_context_bind_parent_child(struct intel_context *parent, + struct intel_context *child); + +#define for_each_child(parent, ce)\ + list_for_each_entry(ce, &(parent)->guc_child_list, guc_child_link) +#define for_each_child_safe(parent, ce, cn)\ + list_for_each_entry_safe(ce, cn, &(parent)->guc_child_list, guc_child_link) + /** * intel_context_lock_pinned - Stablises the 'pinned' status of the HW context * @ce - the context diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index fd338a30617e..0fafc178cf2c 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -213,6 +213,29 @@ struct intel_context { */ struct list_head destroyed_link; + /** anonymous struct for parent / children only members */ + struct { + union { + /** + * @guc_child_list: parent's list of of children + * contexts, no protection as immutable after context + * creation + */ + struct list_head guc_child_list; + /** + * @guc_child_link: child's link into parent's list of + * children + */ + struct list_head guc_child_link; + }; + + /** @parent: pointer to parent if child */ + struct intel_context *parent; + + /** @guc_number_children: number of children if parent */ + u8 guc_number_children; + }; + #ifdef CONFIG_DRM_I915_SELFTEST /** * @drop_schedule_enable: Force drop of schedule enable G2H for selftest -- 2.32.0
next prev parent reply other threads:[~2021-08-20 22:51 UTC|newest] Thread overview: 145+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-20 22:44 [PATCH 00/27] Parallel submission aka multi-bb execbuf Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-20 22:44 ` [PATCH 01/27] drm/i915/guc: Squash Clean up GuC CI failures, simplify locking, and kernel DOC Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-20 22:44 ` [PATCH 02/27] drm/i915/guc: Allow flexible number of context ids Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-09 22:13 ` John Harrison 2021-09-10 0:14 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 03/27] drm/i915/guc: Connect the number of guc_ids to debugfs Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-09 22:16 ` John Harrison 2021-09-10 0:16 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 04/27] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-09 22:28 ` John Harrison 2021-09-10 0:21 ` Matthew Brost 2021-09-13 9:55 ` Tvrtko Ursulin 2021-09-13 17:12 ` Matthew Brost 2021-09-14 8:41 ` Tvrtko Ursulin 2021-08-20 22:44 ` [PATCH 05/27] drm/i915: Add GT PM unpark worker Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-09 22:36 ` John Harrison 2021-09-10 0:34 ` Matthew Brost 2021-09-10 8:36 ` Tvrtko Ursulin 2021-09-10 20:09 ` Matthew Brost 2021-09-13 10:33 ` Tvrtko Ursulin 2021-09-13 17:20 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 06/27] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-09 22:46 ` John Harrison 2021-09-10 0:41 ` Matthew Brost 2021-09-13 22:26 ` John Harrison 2021-09-14 1:12 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 07/27] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-09 22:51 ` John Harrison 2021-09-13 16:54 ` Matthew Brost 2021-09-13 22:38 ` John Harrison 2021-09-14 5:02 ` Matthew Brost 2021-09-13 16:55 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 08/27] drm/i915: Add logical engine mapping Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-10 11:12 ` Tvrtko Ursulin 2021-09-10 19:49 ` Matthew Brost 2021-09-13 9:24 ` Tvrtko Ursulin 2021-09-13 16:50 ` Matthew Brost 2021-09-14 8:34 ` Tvrtko Ursulin 2021-09-14 18:04 ` Matthew Brost 2021-09-15 8:24 ` Tvrtko Ursulin 2021-09-15 16:58 ` Matthew Brost 2021-09-16 8:31 ` Tvrtko Ursulin 2021-08-20 22:44 ` [PATCH 09/27] drm/i915: Expose logical engine instance to user Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-13 23:06 ` John Harrison 2021-09-14 1:08 ` Matthew Brost 2021-08-20 22:44 ` Matthew Brost [this message] 2021-08-20 22:44 ` [Intel-gfx] [PATCH 10/27] drm/i915/guc: Introduce context parent-child relationship Matthew Brost 2021-09-13 23:19 ` John Harrison 2021-09-14 1:18 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 11/27] drm/i915/guc: Implement parallel context pin / unpin functions Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-20 22:44 ` [PATCH 12/27] drm/i915/guc: Add multi-lrc context registration Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-15 19:21 ` John Harrison 2021-09-15 19:31 ` Matthew Brost 2021-09-15 20:23 ` John Harrison 2021-09-15 20:33 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 13/27] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-15 19:24 ` John Harrison 2021-09-15 19:34 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 14/27] drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-15 20:04 ` John Harrison 2021-09-15 20:55 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 15/27] drm/i915/guc: Implement multi-lrc submission Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-21 14:04 ` kernel test robot 2021-08-21 14:04 ` kernel test robot 2021-08-21 14:04 ` kernel test robot 2021-08-22 2:18 ` kernel test robot 2021-08-22 2:18 ` kernel test robot 2021-08-22 2:18 ` [Intel-gfx] " kernel test robot 2021-09-20 21:48 ` John Harrison 2021-09-22 16:25 ` Matthew Brost 2021-09-22 20:15 ` John Harrison 2021-09-23 2:44 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 16/27] drm/i915/guc: Insert submit fences between requests in parent-child relationship Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-20 21:57 ` John Harrison 2021-08-20 22:44 ` [PATCH 17/27] drm/i915/guc: Implement multi-lrc reset Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-20 22:44 ` John Harrison 2021-09-22 16:16 ` Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] [PATCH 18/27] drm/i915/guc: Update debugfs for GuC multi-lrc Matthew Brost 2021-08-20 22:44 ` Matthew Brost 2021-09-20 22:48 ` [Intel-gfx] " John Harrison 2021-09-21 19:13 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 19/27] drm/i915: Fix bug in user proto-context creation that leaked contexts Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-20 22:57 ` John Harrison 2021-09-21 14:49 ` Tvrtko Ursulin 2021-09-21 19:28 ` Matthew Brost 2021-09-21 19:28 ` Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] [PATCH 20/27] drm/i915/guc: Connect UAPI to GuC multi-lrc interface Matthew Brost 2021-08-20 22:44 ` Matthew Brost 2021-08-29 4:00 ` [Intel-gfx] " kernel test robot 2021-08-29 4:00 ` kernel test robot 2021-08-29 19:59 ` kernel test robot 2021-08-29 19:59 ` kernel test robot 2021-09-21 0:09 ` John Harrison 2021-09-22 16:38 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 21/27] drm/i915/doc: Update parallel submit doc to point to i915_drm.h Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-21 0:12 ` John Harrison 2021-08-20 22:44 ` [PATCH 22/27] drm/i915/guc: Add basic GuC multi-lrc selftest Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-28 20:47 ` John Harrison 2021-08-20 22:44 ` [PATCH 23/27] drm/i915/guc: Implement no mid batch preemption for multi-lrc Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-10 11:25 ` Tvrtko Ursulin 2021-09-10 20:49 ` Matthew Brost 2021-09-13 10:52 ` Tvrtko Ursulin 2021-09-28 22:20 ` John Harrison 2021-09-28 22:33 ` Matthew Brost 2021-09-28 23:33 ` John Harrison 2021-09-29 0:22 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 24/27] drm/i915: Multi-BB execbuf Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-21 19:01 ` kernel test robot 2021-08-21 19:01 ` kernel test robot 2021-08-30 3:46 ` kernel test robot 2021-08-30 3:46 ` kernel test robot 2021-09-30 22:16 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 25/27] drm/i915/guc: Handle errors in multi-lrc requests Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-09-29 20:44 ` John Harrison 2021-09-29 20:58 ` Matthew Brost 2021-08-20 22:44 ` [PATCH 26/27] drm/i915: Enable multi-bb execbuf Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-20 22:44 ` [PATCH 27/27] drm/i915/execlists: Weak parallel submission support for execlists Matthew Brost 2021-08-20 22:44 ` [Intel-gfx] " Matthew Brost 2021-08-20 23:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Parallel submission aka multi-bb execbuf (rev3) Patchwork 2021-08-20 23:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-08-20 23:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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