From: Dave Airlie <airlied@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@linux.intel.com, Dave Airlie <airlied@redhat.com>,
Jani Nikula <jani.nikula@intel.com>
Subject: [Intel-gfx] [PATCH 19/23] drm/i915: constify the cdclk vtable
Date: Thu, 9 Sep 2021 11:10:56 +1000 [thread overview]
Message-ID: <20210909011100.2987971-20-airlied@gmail.com> (raw)
In-Reply-To: <20210909011100.2987971-1-airlied@gmail.com>
From: Dave Airlie <airlied@redhat.com>
This is a bit of a twisty one since each platform is slightly
different, so might take some more review care.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 300 ++++++++++++++-------
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 206 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 27a4a226aa49..f501c748458e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
+ dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
}
int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
+ return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_config)
{
- return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
+ return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
+ return dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
+ if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2886,6 +2886,157 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static struct intel_cdclk_funcs tgl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs ehl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = ehl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs icl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = icl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs bxt_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = bxt_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs skl_cdclk_funcs = {
+ .get_cdclk = skl_get_cdclk,
+ .set_cdclk = skl_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = skl_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs bdw_cdclk_funcs = {
+ .get_cdclk = bdw_get_cdclk,
+ .set_cdclk = bdw_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs chv_cdclk_funcs = {
+ .get_cdclk = vlv_get_cdclk,
+ .set_cdclk = chv_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs vlv_cdclk_funcs = {
+ .get_cdclk = vlv_get_cdclk,
+ .set_cdclk = vlv_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs hsw_cdclk_funcs = {
+ .get_cdclk = hsw_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+/* SNB, IVB, 965G, 945G */
+static struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
+ .get_cdclk = fixed_400mhz_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs ilk_cdclk_funcs = {
+ .get_cdclk = fixed_450mhz_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs gm45_cdclk_funcs = {
+ .get_cdclk = gm45_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+/* G45 uses G33 */
+
+static struct intel_cdclk_funcs i965gm_cdclk_funcs = {
+ .get_cdclk = i965gm_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+/* i965G uses fixed 400 */
+
+static struct intel_cdclk_funcs pnv_cdclk_funcs = {
+ .get_cdclk = pnv_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs g33_cdclk_funcs = {
+ .get_cdclk = g33_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs i945gm_cdclk_funcs = {
+ .get_cdclk = i945gm_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+/* i945G uses fixed 400 */
+
+static struct intel_cdclk_funcs i915gm_cdclk_funcs = {
+ .get_cdclk = i915gm_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs i915g_cdclk_funcs = {
+ .get_cdclk = fixed_333mhz_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs i865g_cdclk_funcs = {
+ .get_cdclk = fixed_266mhz_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs i85x_cdclk_funcs = {
+ .get_cdclk = i85x_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs i845g_cdclk_funcs = {
+ .get_cdclk = fixed_200mhz_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs i830_cdclk_funcs = {
+ .get_cdclk = fixed_133mhz_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
/**
* intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
* @dev_priv: i915 device
@@ -2893,119 +3044,78 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
dev_priv->cdclk.table = rkl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 12) {
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_JSL_EHL(dev_priv)) {
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = ehl_calc_voltage_level;
+ dev_priv->cdclk_funcs = &ehl_cdclk_funcs;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = icl_calc_voltage_level;
+ dev_priv->cdclk_funcs = &icl_cdclk_funcs;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = bxt_calc_voltage_level;
+ dev_priv->cdclk_funcs = &bxt_cdclk_funcs;
if (IS_GEMINILAKE(dev_priv))
dev_priv->cdclk.table = glk_cdclk_table;
else
dev_priv->cdclk.table = bxt_cdclk_table;
} else if (DISPLAY_VER(dev_priv) == 9) {
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.set_cdclk = skl_set_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = skl_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs = &skl_cdclk_funcs;
} else if (IS_BROADWELL(dev_priv)) {
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.set_cdclk = bdw_set_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs = &bdw_cdclk_funcs;
+ } else if (IS_HASWELL(dev_priv)) {
+ dev_priv->cdclk_funcs = &hsw_cdclk_funcs;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.set_cdclk = chv_set_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs = &chv_cdclk_funcs;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.set_cdclk = vlv_set_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
- } else {
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs = &vlv_cdclk_funcs;
+ } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
+ dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
+ } else if (IS_IRONLAKE(dev_priv)) {
+ dev_priv->cdclk_funcs = &ilk_cdclk_funcs;
+ } else if (IS_GM45(dev_priv)) {
+ dev_priv->cdclk_funcs = &gm45_cdclk_funcs;
+ } else if (IS_G45(dev_priv)) {
+ dev_priv->cdclk_funcs = &g33_cdclk_funcs;
+ } else if (IS_I965GM(dev_priv)) {
+ dev_priv->cdclk_funcs = &i965gm_cdclk_funcs;
+ } else if (IS_I965G(dev_priv)) {
+ dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
+ } else if (IS_PINEVIEW(dev_priv)) {
+ dev_priv->cdclk_funcs = &pnv_cdclk_funcs;
+ } else if (IS_G33(dev_priv)) {
+ dev_priv->cdclk_funcs = &g33_cdclk_funcs;
+ } else if (IS_I945GM(dev_priv)) {
+ dev_priv->cdclk_funcs = &i945gm_cdclk_funcs;
+ } else if (IS_I945G(dev_priv)) {
+ dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
+ } else if (IS_I915GM(dev_priv)) {
+ dev_priv->cdclk_funcs = &i915gm_cdclk_funcs;
+ } else if (IS_I915G(dev_priv)) {
+ dev_priv->cdclk_funcs = &i915g_cdclk_funcs;
+ } else if (IS_I865G(dev_priv)) {
+ dev_priv->cdclk_funcs = &i865g_cdclk_funcs;
+ } else if (IS_I85X(dev_priv)) {
+ dev_priv->cdclk_funcs = &i85x_cdclk_funcs;
+ } else if (IS_I845G(dev_priv)) {
+ dev_priv->cdclk_funcs = &i845g_cdclk_funcs;
+ } else if (IS_I830(dev_priv)) {
+ dev_priv->cdclk_funcs = &i830_cdclk_funcs;
}
- if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = bxt_get_cdclk;
- else if (DISPLAY_VER(dev_priv) == 9)
- dev_priv->cdclk_funcs.get_cdclk = skl_get_cdclk;
- else if (IS_BROADWELL(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = bdw_get_cdclk;
- else if (IS_HASWELL(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = hsw_get_cdclk;
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = vlv_get_cdclk;
- else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
- else if (IS_IRONLAKE(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_450mhz_get_cdclk;
- else if (IS_GM45(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = gm45_get_cdclk;
- else if (IS_G45(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
- else if (IS_I965GM(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = i965gm_get_cdclk;
- else if (IS_I965G(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
- else if (IS_PINEVIEW(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = pnv_get_cdclk;
- else if (IS_G33(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
- else if (IS_I945GM(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = i945gm_get_cdclk;
- else if (IS_I945G(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
- else if (IS_I915GM(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = i915gm_get_cdclk;
- else if (IS_I915G(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_333mhz_get_cdclk;
- else if (IS_I865G(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_266mhz_get_cdclk;
- else if (IS_I85X(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = i85x_get_cdclk;
- else if (IS_I845G(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_200mhz_get_cdclk;
- else if (IS_I830(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
-
- if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs.get_cdclk,
- "Unknown platform. Assuming 133 MHz CDCLK\n"))
- dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
+ if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs,
+ "Unknown platform. Assuming i830\n"))
+ dev_priv->cdclk_funcs = &i830_cdclk_funcs;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5ed624b9c3cc..b2c63ed5b8fe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1006,7 +1006,7 @@ struct drm_i915_private {
const struct intel_audio_funcs *audio_funcs;
/* Display CDCLK functions */
- struct intel_cdclk_funcs cdclk_funcs;
+ const struct intel_cdclk_funcs *cdclk_funcs;
/* PCH chipset type */
enum intel_pch pch_type;
--
2.31.1
next prev parent reply other threads:[~2021-09-09 1:11 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-09 1:10 [Intel-gfx] [PATCH 00/23] i915/display: split and constify vtable (v2) Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 01/23] drm/i915/pm: drop get_fifo_size vfunc Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 02/23] drm/i915: make update_wm take a dev_priv Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 03/23] drm/i915/wm: provide wrappers around watermark vfuncs calls Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 04/23] drm/i915: add wrappers around cdclk vtable funcs Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 05/23] drm/i915/display: add intel_fdi_link_train wrapper Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 06/23] drm/i915: split clock gating init from display vtable Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 07/23] drm/i915: split watermark vfuncs " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 08/23] drm/i915: split color functions " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 09/23] drm/i915: split audio " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 10/23] drm/i915: split cdclk " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 11/23] drm/i915: split irq hotplug function " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 12/23] drm/i915: split fdi link training " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 13/23] drm/i915: split the dpll clock compute out " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 14/23] drm/i915: constify fdi link training vtable Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 15/23] drm/i915: constify hotplug function vtable Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 16/23] drm/i915: constify color " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 17/23] drm/i915: constify the audio " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 18/23] drm/i915: constify the dpll clock vtable Dave Airlie
2021-09-09 1:10 ` Dave Airlie [this message]
2021-09-09 1:10 ` [Intel-gfx] [PATCH 20/23] drm/i915: drop unused function ptr and comments Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 21/23] drm/i915: constify display function vtable Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 22/23] drm/i915: constify clock gating init vtable Dave Airlie
2021-09-09 1:11 ` [Intel-gfx] [PATCH 23/23] drm/i915: constify display wm vtable Dave Airlie
2021-09-09 1:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915/display: split and constify vtable (rev2) Patchwork
2021-09-09 1:47 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-09-09 2:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-09-09 1:52 [Intel-gfx] [PATCH 00/23] i915/display: split and constify vtable (v3) Dave Airlie
2021-09-09 1:53 ` [Intel-gfx] [PATCH 19/23] drm/i915: constify the cdclk vtable Dave Airlie
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210909011100.2987971-20-airlied@gmail.com \
--to=airlied@gmail.com \
--cc=airlied@redhat.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
--cc=jani.nikula@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.