From: Dave Airlie <airlied@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@linux.intel.com, Dave Airlie <airlied@redhat.com>
Subject: [Intel-gfx] [PATCH 04/23] drm/i915: add wrappers around cdclk vtable funcs.
Date: Thu, 9 Sep 2021 11:10:41 +1000 [thread overview]
Message-ID: <20210909011100.2987971-5-airlied@gmail.com> (raw)
In-Reply-To: <20210909011100.2987971-1-airlied@gmail.com>
From: Dave Airlie <airlied@redhat.com>
This adds wrappers around all the vtable callers so they are in
one place.
Suggested by Jani.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 47 +++++++++++++++----
drivers/gpu/drm/i915/display/intel_cdclk.h | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_power.c | 2 +-
4 files changed, 44 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9aec17b33819..0e09f259914f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -59,6 +59,37 @@
* dividers can be programmed correctly.
*/
+void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_config *cdclk_config)
+{
+ dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+}
+
+int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ return dev_priv->display.bw_calc_min_cdclk(state);
+}
+
+static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
+{
+ dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+}
+
+static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_state *cdclk_config)
+{
+ return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+}
+
+static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
+ int cdclk)
+{
+ return dev_priv->display.calc_voltage_level(cdclk);
+}
+
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
@@ -1466,7 +1497,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
* at least what the CDCLK frequency requires.
*/
cdclk_config->voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
}
static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1777,7 +1808,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
@@ -1789,7 +1820,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
@@ -1956,7 +1987,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
&dev_priv->gmbus_mutex);
}
- dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+ intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
for_each_intel_dp(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2424,7 +2455,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
cdclk_state->logical.cdclk = cdclk;
cdclk_state->logical.voltage_level =
max_t(int, min_voltage_level,
- dev_priv->display.calc_voltage_level(cdclk));
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk));
if (!cdclk_state->active_pipes) {
cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
@@ -2433,7 +2464,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
cdclk_state->actual.vco = vco;
cdclk_state->actual.cdclk = cdclk;
cdclk_state->actual.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk);
} else {
cdclk_state->actual = cdclk_state->logical;
}
@@ -2525,7 +2556,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
new_cdclk_state->active_pipes =
intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
- ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
+ ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state);
if (ret)
return ret;
@@ -2705,7 +2736,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
*/
void intel_update_cdclk(struct drm_i915_private *dev_priv)
{
- dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
+ intel_cdclk_get_cdclk(dev_priv, &dev_priv->cdclk.hw);
/*
* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index b34eb00fb327..309b3f394e24 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -68,7 +68,9 @@ void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
const char *context);
int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
-
+void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_config *cdclk_config);
+int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state);
struct intel_cdclk_state *
intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3d8afa9f3237..8d2147880fa1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9146,7 +9146,7 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
*need_cdclk_calc = true;
- ret = dev_priv->display.bw_calc_min_cdclk(state);
+ ret = intel_cdclk_bw_calc_min_cdclk(state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cce1a926fcc1..a274e2b33e91 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1195,7 +1195,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- dev_priv->display.get_cdclk(dev_priv, &cdclk_config);
+ intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
drm_WARN_ON(&dev_priv->drm,
intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
--
2.31.1
next prev parent reply other threads:[~2021-09-09 1:11 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-09 1:10 [Intel-gfx] [PATCH 00/23] i915/display: split and constify vtable (v2) Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 01/23] drm/i915/pm: drop get_fifo_size vfunc Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 02/23] drm/i915: make update_wm take a dev_priv Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 03/23] drm/i915/wm: provide wrappers around watermark vfuncs calls Dave Airlie
2021-09-09 1:10 ` Dave Airlie [this message]
2021-09-09 1:10 ` [Intel-gfx] [PATCH 05/23] drm/i915/display: add intel_fdi_link_train wrapper Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 06/23] drm/i915: split clock gating init from display vtable Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 07/23] drm/i915: split watermark vfuncs " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 08/23] drm/i915: split color functions " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 09/23] drm/i915: split audio " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 10/23] drm/i915: split cdclk " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 11/23] drm/i915: split irq hotplug function " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 12/23] drm/i915: split fdi link training " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 13/23] drm/i915: split the dpll clock compute out " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 14/23] drm/i915: constify fdi link training vtable Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 15/23] drm/i915: constify hotplug function vtable Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 16/23] drm/i915: constify color " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 17/23] drm/i915: constify the audio " Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 18/23] drm/i915: constify the dpll clock vtable Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 19/23] drm/i915: constify the cdclk vtable Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 20/23] drm/i915: drop unused function ptr and comments Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 21/23] drm/i915: constify display function vtable Dave Airlie
2021-09-09 1:10 ` [Intel-gfx] [PATCH 22/23] drm/i915: constify clock gating init vtable Dave Airlie
2021-09-09 1:11 ` [Intel-gfx] [PATCH 23/23] drm/i915: constify display wm vtable Dave Airlie
2021-09-09 1:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915/display: split and constify vtable (rev2) Patchwork
2021-09-09 1:47 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-09-09 2:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-09-09 1:52 [Intel-gfx] [PATCH 00/23] i915/display: split and constify vtable (v3) Dave Airlie
2021-09-09 1:53 ` [Intel-gfx] [PATCH 04/23] drm/i915: add wrappers around cdclk vtable funcs Dave Airlie
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