From: Alexey Baturo <baturo.alexey@gmail.com> Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com, palmer@dabbelt.com Subject: [PATCH v11 0/7] RISC-V Pointer Masking implementation Date: Thu, 9 Sep 2021 22:00:26 +0300 [thread overview] Message-ID: <20210909190033.1339448-1-space.monkey.delivers@gmail.com> (raw) v10: Hi folks, For this iteration I fixes some minor things Alistair mentioned in review and splitted one of patches into two: one with preliminary CSR numbers(unfortunately there're still no final ones) and another with actual CSR implementation. As for not raising the exception on writing into PM CSRs in wrong mode, it's expected behavior and reflected in the spec, but I agree that it's odd. Thanks v9: Hi folks, Finaly the J-ext spec has table with preliminary CSR numbers. Rebased and updated CSR machinery for recent changes. Addressed Alistair's comments. v8-resend: Resending to trigger recheck due to minor codestyle issues. v8: Hi folks, Finally we were able to assign v0.1 draft for Pointer Masking extension for RISC-V: https://github.com/riscv/riscv-j-extension/blob/master/pointer-masking-proposal.adoc This is supposed to be the first series of patches with initial support for PM. It obviously misses support for hypervisor mode, vector load/stores and some other features, while using temporary csr numbers(they're to be assigned by the committee a bit later). With this patch series we were able to run a bunch of tests with HWASAN checks enabled. I hope I've managed to addressed @Alistair's previous comments in this version. Thanks! v7: Hi folks, Sorry it took me almost 3 month to provide the reply and fixes: it was a really busy EOY. This series contains fixed @Alistair suggestion on enabling J-ext. As for @Richard comments: - Indeed I've missed appending review-by to the approved commits. Now I've restored them except for the fourth commit. @Richard could you please tell if you think it's still ok to commit it as is, or should I support masking mem ops for RVV first? - These patches don't have any support for load/store masking for RVV and RVH extensions, so no support for special load/store for Hypervisor in particular. If this patch series would be accepted, I think my further attention would be to: - Support pm for memory operations for RVV - Add proper csr and support pm for memory operations for Hypervisor mode - Support address wrapping on unaligned accesses as @Richard mentioned previously Thanks! Alexey Baturo (6): [RISCV_PM] Add J-extension into RISC-V [RISCV_PM] Add CSR defines for RISC-V PM extension [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode [RISCV_PM] Print new PM CSRs in QEMU logs [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions [RISCV_PM] Allow experimental J-ext to be turned on Anatoly Parshintsev (1): [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension target/riscv/cpu.c | 31 +++ target/riscv/cpu.h | 33 +++ target/riscv/cpu_bits.h | 96 ++++++++ target/riscv/csr.c | 287 ++++++++++++++++++++++++ target/riscv/insn_trans/trans_rva.c.inc | 3 + target/riscv/insn_trans/trans_rvd.c.inc | 2 + target/riscv/insn_trans/trans_rvf.c.inc | 2 + target/riscv/insn_trans/trans_rvi.c.inc | 2 + target/riscv/translate.c | 42 ++++ 9 files changed, 498 insertions(+) -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Alexey Baturo <baturo.alexey@gmail.com> Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, space.monkey.delivers@gmail.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v11 0/7] RISC-V Pointer Masking implementation Date: Thu, 9 Sep 2021 22:00:26 +0300 [thread overview] Message-ID: <20210909190033.1339448-1-space.monkey.delivers@gmail.com> (raw) v10: Hi folks, For this iteration I fixes some minor things Alistair mentioned in review and splitted one of patches into two: one with preliminary CSR numbers(unfortunately there're still no final ones) and another with actual CSR implementation. As for not raising the exception on writing into PM CSRs in wrong mode, it's expected behavior and reflected in the spec, but I agree that it's odd. Thanks v9: Hi folks, Finaly the J-ext spec has table with preliminary CSR numbers. Rebased and updated CSR machinery for recent changes. Addressed Alistair's comments. v8-resend: Resending to trigger recheck due to minor codestyle issues. v8: Hi folks, Finally we were able to assign v0.1 draft for Pointer Masking extension for RISC-V: https://github.com/riscv/riscv-j-extension/blob/master/pointer-masking-proposal.adoc This is supposed to be the first series of patches with initial support for PM. It obviously misses support for hypervisor mode, vector load/stores and some other features, while using temporary csr numbers(they're to be assigned by the committee a bit later). With this patch series we were able to run a bunch of tests with HWASAN checks enabled. I hope I've managed to addressed @Alistair's previous comments in this version. Thanks! v7: Hi folks, Sorry it took me almost 3 month to provide the reply and fixes: it was a really busy EOY. This series contains fixed @Alistair suggestion on enabling J-ext. As for @Richard comments: - Indeed I've missed appending review-by to the approved commits. Now I've restored them except for the fourth commit. @Richard could you please tell if you think it's still ok to commit it as is, or should I support masking mem ops for RVV first? - These patches don't have any support for load/store masking for RVV and RVH extensions, so no support for special load/store for Hypervisor in particular. If this patch series would be accepted, I think my further attention would be to: - Support pm for memory operations for RVV - Add proper csr and support pm for memory operations for Hypervisor mode - Support address wrapping on unaligned accesses as @Richard mentioned previously Thanks! Alexey Baturo (6): [RISCV_PM] Add J-extension into RISC-V [RISCV_PM] Add CSR defines for RISC-V PM extension [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode [RISCV_PM] Print new PM CSRs in QEMU logs [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions [RISCV_PM] Allow experimental J-ext to be turned on Anatoly Parshintsev (1): [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension target/riscv/cpu.c | 31 +++ target/riscv/cpu.h | 33 +++ target/riscv/cpu_bits.h | 96 ++++++++ target/riscv/csr.c | 287 ++++++++++++++++++++++++ target/riscv/insn_trans/trans_rva.c.inc | 3 + target/riscv/insn_trans/trans_rvd.c.inc | 2 + target/riscv/insn_trans/trans_rvf.c.inc | 2 + target/riscv/insn_trans/trans_rvi.c.inc | 2 + target/riscv/translate.c | 42 ++++ 9 files changed, 498 insertions(+) -- 2.30.2
next reply other threads:[~2021-09-09 19:03 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-09 19:00 Alexey Baturo [this message] 2021-09-09 19:00 ` [PATCH v11 0/7] RISC-V Pointer Masking implementation Alexey Baturo 2021-09-09 19:00 ` [PATCH v11 1/7] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo 2021-09-09 19:00 ` Alexey Baturo 2021-09-10 7:15 ` Bin Meng 2021-09-09 19:00 ` [PATCH v11 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension Alexey Baturo 2021-09-09 19:00 ` Alexey Baturo 2021-09-09 19:00 ` [PATCH v11 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo 2021-09-09 19:00 ` Alexey Baturo 2021-09-09 19:00 ` [PATCH v11 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo 2021-09-09 19:00 ` Alexey Baturo 2021-09-09 19:00 ` [PATCH v11 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo 2021-09-09 19:00 ` Alexey Baturo 2021-09-09 22:00 ` Richard Henderson 2021-09-09 22:00 ` Richard Henderson 2021-09-18 5:08 ` Alexey Baturo 2021-09-18 5:08 ` Alexey Baturo 2021-09-09 19:00 ` [PATCH v11 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo 2021-09-09 19:00 ` Alexey Baturo 2021-09-09 19:00 ` [PATCH v11 7/7] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo 2021-09-09 19:00 ` Alexey Baturo 2021-09-10 7:14 ` Bin Meng
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