From: Kishon Vijay Abraham I <kishon@ti.com>
To: Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>,
Rob Herring <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>, <lokeshvutla@ti.com>
Subject: [PATCH 4/6] arm64: dts: ti: j7200-main: Fix "bus-range" upto 256 bus number for PCIe
Date: Wed, 15 Sep 2021 11:23:56 +0530 [thread overview]
Message-ID: <20210915055358.19997-5-kishon@ti.com> (raw)
In-Reply-To: <20210915055358.19997-1-kishon@ti.com>
commit 3276d9f53cf6 ("arm64: dts: ti: k3-j7200-main: Add PCIe device
tree node") incorrectly added PCIe bus numbers from 0 to 15 (copy-paste
from J721E node). Enable all the supported bus numbers from 0 to 255
defined in PCIe spec here.
Fixes: 3276d9f53cf6 ("arm64: dts: ti: k3-j7200-main: Add PCIe device tree node")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 521a56316fa5..874cba75e9a5 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -606,7 +606,7 @@
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x0 0xff>;
cdns,no-bar-match-nbits = <64>;
vendor-id = <0x104c>;
device-id = <0xb00f>;
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>,
Rob Herring <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>, <lokeshvutla@ti.com>
Subject: [PATCH 4/6] arm64: dts: ti: j7200-main: Fix "bus-range" upto 256 bus number for PCIe
Date: Wed, 15 Sep 2021 11:23:56 +0530 [thread overview]
Message-ID: <20210915055358.19997-5-kishon@ti.com> (raw)
In-Reply-To: <20210915055358.19997-1-kishon@ti.com>
commit 3276d9f53cf6 ("arm64: dts: ti: k3-j7200-main: Add PCIe device
tree node") incorrectly added PCIe bus numbers from 0 to 15 (copy-paste
from J721E node). Enable all the supported bus numbers from 0 to 255
defined in PCIe spec here.
Fixes: 3276d9f53cf6 ("arm64: dts: ti: k3-j7200-main: Add PCIe device tree node")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 521a56316fa5..874cba75e9a5 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -606,7 +606,7 @@
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x0 0xff>;
cdns,no-bar-match-nbits = <64>;
vendor-id = <0x104c>;
device-id = <0xb00f>;
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-09-15 5:54 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-15 5:53 [PATCH 0/6] AM65/J7200/J721E: Misc PCIe DT fixes Kishon Vijay Abraham I
2021-09-15 5:53 ` Kishon Vijay Abraham I
2021-09-15 5:53 ` [PATCH 1/6] arm64: dts: ti: k3-j721e-main: Fix "max-virtual-functions" in PCIe EP nodes Kishon Vijay Abraham I
2021-09-15 5:53 ` Kishon Vijay Abraham I
2021-09-15 5:53 ` [PATCH 2/6] arm64: dts: ti: k3-j721e-main: Fix "bus-range" upto 256 bus number for PCIe Kishon Vijay Abraham I
2021-09-15 5:53 ` Kishon Vijay Abraham I
2021-09-15 5:53 ` [PATCH 3/6] arm64: dts: ti: j7200-main: Fix "vendor-id"/"device-id" properties of pcie node Kishon Vijay Abraham I
2021-09-15 5:53 ` Kishon Vijay Abraham I
2021-09-15 5:53 ` Kishon Vijay Abraham I [this message]
2021-09-15 5:53 ` [PATCH 4/6] arm64: dts: ti: j7200-main: Fix "bus-range" upto 256 bus number for PCIe Kishon Vijay Abraham I
2021-09-15 5:53 ` [PATCH 5/6] arm64: dts: ti: j7200-main: Add *max-virtual-functions* for pcie-ep DT node Kishon Vijay Abraham I
2021-09-15 5:53 ` Kishon Vijay Abraham I
2021-09-15 5:53 ` [PATCH 6/6] arm64: dts: ti: k3-am65-main: Cleanup "ranges" property in "pcie" " Kishon Vijay Abraham I
2021-09-15 5:53 ` Kishon Vijay Abraham I
2021-09-15 10:50 ` [PATCH 0/6] AM65/J7200/J721E: Misc PCIe DT fixes Aswath Govindraju
2021-09-15 10:50 ` Aswath Govindraju
2021-09-20 18:59 ` Nishanth Menon
2021-09-20 18:59 ` Nishanth Menon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210915055358.19997-5-kishon@ti.com \
--to=kishon@ti.com \
--cc=devicetree@vger.kernel.org \
--cc=kristo@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lokeshvutla@ti.com \
--cc=nm@ti.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.