From: Kewei Xu <kewei.xu@mediatek.com>
To: <wsa@the-dreams.de>
Cc: <matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
<linux-i2c@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <leilk.liu@mediatek.com>,
<qii.wang@mediatek.com>, <liguo.zhang@mediatek.com>,
<caiyu.chen@mediatek.com>, <ot_daolong.zhu@mediatek.com>,
<yuhan.wei@mediatek.com>, <kewei.xu@mediatek.com>
Subject: [PATCH v7 2/7] i2c: mediatek: Reset the handshake signal between i2c and dma
Date: Fri, 17 Sep 2021 18:14:11 +0800 [thread overview]
Message-ID: <20210917101416.20760-3-kewei.xu@mediatek.com> (raw)
In-Reply-To: <20210917101416.20760-1-kewei.xu@mediatek.com>
Due to changes in the hardware design of the handshaking signal
between i2c and dma, it is necessary to reset the handshaking
signal before each transfer to ensure that the multi-msgs can
be transferred correctly.
Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 32518081b5a4..08ce8a417bed 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -15,6 +15,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
@@ -47,6 +48,9 @@
#define I2C_RD_TRANAC_VALUE 0x0001
#define I2C_SCL_MIS_COMP_VALUE 0x0000
#define I2C_CHN_CLR_FLAG 0x0000
+#define I2C_CLR_DEBUGCTR 0x0000
+#define I2C_RELIABILITY 0x0010
+#define I2C_DMAACK_ENABLE 0x0008
#define I2C_DMA_CON_TX 0x0000
#define I2C_DMA_CON_RX 0x0001
@@ -842,6 +846,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
u16 restart_flag = 0;
u16 dma_sync = 0;
u32 reg_4g_mode;
+ u32 reg_dma_reset;
u8 *dma_rd_buf = NULL;
u8 *dma_wr_buf = NULL;
dma_addr_t rpaddr = 0;
@@ -855,6 +860,27 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
reinit_completion(&i2c->msg_complete);
+ if (i2c->dev_comp->apdma_sync && i2c->op != I2C_MASTER_WRRD && num > 1) {
+ mtk_i2c_writew(i2c, I2C_CLR_DEBUGCTR, OFFSET_DEBUGCTRL);
+ writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST,
+ i2c->pdmabase + OFFSET_RST);
+
+ ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST,
+ reg_dma_reset,
+ !(reg_dma_reset & I2C_DMA_WARM_RST),
+ 0, 100);
+ if (ret) {
+ dev_err(i2c->dev, "DMA warm reset timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
+ mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET);
+ mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
+ mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE,
+ OFFSET_DEBUGCTRL);
+ }
+
control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Kewei Xu <kewei.xu@mediatek.com>
To: <wsa@the-dreams.de>
Cc: <matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
<linux-i2c@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <leilk.liu@mediatek.com>,
<qii.wang@mediatek.com>, <liguo.zhang@mediatek.com>,
<caiyu.chen@mediatek.com>, <ot_daolong.zhu@mediatek.com>,
<yuhan.wei@mediatek.com>, <kewei.xu@mediatek.com>
Subject: [PATCH v7 2/7] i2c: mediatek: Reset the handshake signal between i2c and dma
Date: Fri, 17 Sep 2021 18:14:11 +0800 [thread overview]
Message-ID: <20210917101416.20760-3-kewei.xu@mediatek.com> (raw)
In-Reply-To: <20210917101416.20760-1-kewei.xu@mediatek.com>
Due to changes in the hardware design of the handshaking signal
between i2c and dma, it is necessary to reset the handshaking
signal before each transfer to ensure that the multi-msgs can
be transferred correctly.
Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 32518081b5a4..08ce8a417bed 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -15,6 +15,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
@@ -47,6 +48,9 @@
#define I2C_RD_TRANAC_VALUE 0x0001
#define I2C_SCL_MIS_COMP_VALUE 0x0000
#define I2C_CHN_CLR_FLAG 0x0000
+#define I2C_CLR_DEBUGCTR 0x0000
+#define I2C_RELIABILITY 0x0010
+#define I2C_DMAACK_ENABLE 0x0008
#define I2C_DMA_CON_TX 0x0000
#define I2C_DMA_CON_RX 0x0001
@@ -842,6 +846,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
u16 restart_flag = 0;
u16 dma_sync = 0;
u32 reg_4g_mode;
+ u32 reg_dma_reset;
u8 *dma_rd_buf = NULL;
u8 *dma_wr_buf = NULL;
dma_addr_t rpaddr = 0;
@@ -855,6 +860,27 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
reinit_completion(&i2c->msg_complete);
+ if (i2c->dev_comp->apdma_sync && i2c->op != I2C_MASTER_WRRD && num > 1) {
+ mtk_i2c_writew(i2c, I2C_CLR_DEBUGCTR, OFFSET_DEBUGCTRL);
+ writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST,
+ i2c->pdmabase + OFFSET_RST);
+
+ ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST,
+ reg_dma_reset,
+ !(reg_dma_reset & I2C_DMA_WARM_RST),
+ 0, 100);
+ if (ret) {
+ dev_err(i2c->dev, "DMA warm reset timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
+ mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET);
+ mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
+ mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE,
+ OFFSET_DEBUGCTRL);
+ }
+
control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
--
2.25.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Kewei Xu <kewei.xu@mediatek.com>
To: <wsa@the-dreams.de>
Cc: <matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
<linux-i2c@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <leilk.liu@mediatek.com>,
<qii.wang@mediatek.com>, <liguo.zhang@mediatek.com>,
<caiyu.chen@mediatek.com>, <ot_daolong.zhu@mediatek.com>,
<yuhan.wei@mediatek.com>, <kewei.xu@mediatek.com>
Subject: [PATCH v7 2/7] i2c: mediatek: Reset the handshake signal between i2c and dma
Date: Fri, 17 Sep 2021 18:14:11 +0800 [thread overview]
Message-ID: <20210917101416.20760-3-kewei.xu@mediatek.com> (raw)
In-Reply-To: <20210917101416.20760-1-kewei.xu@mediatek.com>
Due to changes in the hardware design of the handshaking signal
between i2c and dma, it is necessary to reset the handshaking
signal before each transfer to ensure that the multi-msgs can
be transferred correctly.
Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 32518081b5a4..08ce8a417bed 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -15,6 +15,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
@@ -47,6 +48,9 @@
#define I2C_RD_TRANAC_VALUE 0x0001
#define I2C_SCL_MIS_COMP_VALUE 0x0000
#define I2C_CHN_CLR_FLAG 0x0000
+#define I2C_CLR_DEBUGCTR 0x0000
+#define I2C_RELIABILITY 0x0010
+#define I2C_DMAACK_ENABLE 0x0008
#define I2C_DMA_CON_TX 0x0000
#define I2C_DMA_CON_RX 0x0001
@@ -842,6 +846,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
u16 restart_flag = 0;
u16 dma_sync = 0;
u32 reg_4g_mode;
+ u32 reg_dma_reset;
u8 *dma_rd_buf = NULL;
u8 *dma_wr_buf = NULL;
dma_addr_t rpaddr = 0;
@@ -855,6 +860,27 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
reinit_completion(&i2c->msg_complete);
+ if (i2c->dev_comp->apdma_sync && i2c->op != I2C_MASTER_WRRD && num > 1) {
+ mtk_i2c_writew(i2c, I2C_CLR_DEBUGCTR, OFFSET_DEBUGCTRL);
+ writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST,
+ i2c->pdmabase + OFFSET_RST);
+
+ ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST,
+ reg_dma_reset,
+ !(reg_dma_reset & I2C_DMA_WARM_RST),
+ 0, 100);
+ if (ret) {
+ dev_err(i2c->dev, "DMA warm reset timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
+ mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET);
+ mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
+ mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE,
+ OFFSET_DEBUGCTRL);
+ }
+
control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-09-17 10:14 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-17 10:14 [PATCH v7 0/7] Introducing an attribute to select the time setting Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-09-17 10:14 ` [PATCH v7 1/7] i2c: mediatek: fixing the incorrect register offset Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-10-02 6:28 ` Wolfram Sang
2021-10-02 6:28 ` Wolfram Sang
2021-10-02 6:28 ` Wolfram Sang
2021-09-17 10:14 ` Kewei Xu [this message]
2021-09-17 10:14 ` [PATCH v7 2/7] i2c: mediatek: Reset the handshake signal between i2c and dma Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-10-02 6:30 ` Wolfram Sang
2021-10-02 6:30 ` Wolfram Sang
2021-10-02 6:30 ` Wolfram Sang
2021-10-08 6:19 ` Kewei Xu
2021-10-08 6:19 ` Kewei Xu
2021-10-08 6:19 ` Kewei Xu
2021-09-17 10:14 ` [PATCH v7 3/7] i2c: mediatek: Dump i2c/dma register when a timeout occurs Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-10-02 6:37 ` Wolfram Sang
2021-10-02 6:37 ` Wolfram Sang
2021-10-02 6:37 ` Wolfram Sang
2021-10-08 7:13 ` Kewei Xu
2021-10-08 7:13 ` Kewei Xu
2021-10-08 7:13 ` Kewei Xu
2021-09-17 10:14 ` [PATCH v7 4/7] dt-bindings: i2c: add attribute use-default-timing Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-09-17 10:14 ` [PATCH v7 5/7] i2c: mediatek: Add OFFSET_EXT_CONF setting back Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-10-02 6:40 ` Wolfram Sang
2021-10-02 6:40 ` Wolfram Sang
2021-10-02 6:40 ` Wolfram Sang
2021-09-17 10:14 ` [PATCH v7 6/7] i2c: mediatek: Isolate speed setting via dts for special devices Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-10-02 6:40 ` Wolfram Sang
2021-10-02 6:40 ` Wolfram Sang
2021-10-02 6:40 ` Wolfram Sang
2021-10-08 8:47 ` Kewei Xu
2021-10-08 8:47 ` Kewei Xu
2021-10-08 8:47 ` Kewei Xu
2021-10-11 10:56 ` Wolfram Sang
2021-10-11 10:56 ` Wolfram Sang
2021-10-11 10:56 ` Wolfram Sang
2021-11-29 12:49 ` Wolfram Sang
2021-11-29 12:49 ` Wolfram Sang
2021-11-29 12:49 ` Wolfram Sang
2021-12-18 9:44 ` Kewei Xu
2021-12-18 9:44 ` Kewei Xu
2021-12-18 9:44 ` Kewei Xu
2021-12-18 10:17 ` Wolfram Sang
2021-12-18 10:17 ` Wolfram Sang
2021-12-18 10:17 ` Wolfram Sang
2021-09-17 10:14 ` [PATCH v7 7/7] i2c: mediatek: modify bus speed calculation formula Kewei Xu
2021-09-17 10:14 ` Kewei Xu
2021-09-17 10:14 ` Kewei Xu
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