From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Cc: <john.c.harrison@intel.com>, <daniele.ceraolospurio@intel.com>
Subject: [PATCH 23/26] drm/i915: Make request conflict tracking understand parallel submits
Date: Mon, 4 Oct 2021 15:06:34 -0700 [thread overview]
Message-ID: <20211004220637.14746-24-matthew.brost@intel.com> (raw)
In-Reply-To: <20211004220637.14746-1-matthew.brost@intel.com>
If an object in the excl or shared slot is a composite fence from a
parallel submit and the current request in the conflict tracking is from
the same parallel context there is no need to enforce ordering as the
ordering already implicit. Make the request conflict tracking understand
this by comparing the parents parallel fence values and skipping the
conflict insertion if the values match.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/i915_request.c | 43 +++++++++++++++++++----------
1 file changed, 29 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index e9bfa32f9270..cf89624020ad 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1325,6 +1325,25 @@ i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
return err;
}
+static inline bool is_parallel_rq(struct i915_request *rq)
+{
+ return intel_context_is_parallel(rq->context);
+}
+
+static inline struct intel_context *request_to_parent(struct i915_request *rq)
+{
+ return intel_context_to_parent(rq->context);
+}
+
+static bool is_same_parallel_context(struct i915_request *to,
+ struct i915_request *from)
+{
+ if (is_parallel_rq(to))
+ return request_to_parent(to) == request_to_parent(from);
+
+ return false;
+}
+
int
i915_request_await_execution(struct i915_request *rq,
struct dma_fence *fence)
@@ -1356,11 +1375,14 @@ i915_request_await_execution(struct i915_request *rq,
* want to run our callback in all cases.
*/
- if (dma_fence_is_i915(fence))
+ if (dma_fence_is_i915(fence)) {
+ if (is_same_parallel_context(rq, to_request(fence)))
+ continue;
ret = __i915_request_await_execution(rq,
to_request(fence));
- else
+ } else {
ret = i915_request_await_external(rq, fence);
+ }
if (ret < 0)
return ret;
} while (--nchild);
@@ -1461,10 +1483,13 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
fence))
continue;
- if (dma_fence_is_i915(fence))
+ if (dma_fence_is_i915(fence)) {
+ if (is_same_parallel_context(rq, to_request(fence)))
+ continue;
ret = i915_request_await_request(rq, to_request(fence));
- else
+ } else {
ret = i915_request_await_external(rq, fence);
+ }
if (ret < 0)
return ret;
@@ -1539,16 +1564,6 @@ i915_request_await_object(struct i915_request *to,
return ret;
}
-static inline bool is_parallel_rq(struct i915_request *rq)
-{
- return intel_context_is_parallel(rq->context);
-}
-
-static inline struct intel_context *request_to_parent(struct i915_request *rq)
-{
- return intel_context_to_parent(rq->context);
-}
-
static struct i915_request *
__i915_request_ensure_parallel_ordering(struct i915_request *rq,
struct intel_timeline *timeline)
--
2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Cc: <john.c.harrison@intel.com>, <daniele.ceraolospurio@intel.com>
Subject: [Intel-gfx] [PATCH 23/26] drm/i915: Make request conflict tracking understand parallel submits
Date: Mon, 4 Oct 2021 15:06:34 -0700 [thread overview]
Message-ID: <20211004220637.14746-24-matthew.brost@intel.com> (raw)
In-Reply-To: <20211004220637.14746-1-matthew.brost@intel.com>
If an object in the excl or shared slot is a composite fence from a
parallel submit and the current request in the conflict tracking is from
the same parallel context there is no need to enforce ordering as the
ordering already implicit. Make the request conflict tracking understand
this by comparing the parents parallel fence values and skipping the
conflict insertion if the values match.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/i915_request.c | 43 +++++++++++++++++++----------
1 file changed, 29 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index e9bfa32f9270..cf89624020ad 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1325,6 +1325,25 @@ i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
return err;
}
+static inline bool is_parallel_rq(struct i915_request *rq)
+{
+ return intel_context_is_parallel(rq->context);
+}
+
+static inline struct intel_context *request_to_parent(struct i915_request *rq)
+{
+ return intel_context_to_parent(rq->context);
+}
+
+static bool is_same_parallel_context(struct i915_request *to,
+ struct i915_request *from)
+{
+ if (is_parallel_rq(to))
+ return request_to_parent(to) == request_to_parent(from);
+
+ return false;
+}
+
int
i915_request_await_execution(struct i915_request *rq,
struct dma_fence *fence)
@@ -1356,11 +1375,14 @@ i915_request_await_execution(struct i915_request *rq,
* want to run our callback in all cases.
*/
- if (dma_fence_is_i915(fence))
+ if (dma_fence_is_i915(fence)) {
+ if (is_same_parallel_context(rq, to_request(fence)))
+ continue;
ret = __i915_request_await_execution(rq,
to_request(fence));
- else
+ } else {
ret = i915_request_await_external(rq, fence);
+ }
if (ret < 0)
return ret;
} while (--nchild);
@@ -1461,10 +1483,13 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
fence))
continue;
- if (dma_fence_is_i915(fence))
+ if (dma_fence_is_i915(fence)) {
+ if (is_same_parallel_context(rq, to_request(fence)))
+ continue;
ret = i915_request_await_request(rq, to_request(fence));
- else
+ } else {
ret = i915_request_await_external(rq, fence);
+ }
if (ret < 0)
return ret;
@@ -1539,16 +1564,6 @@ i915_request_await_object(struct i915_request *to,
return ret;
}
-static inline bool is_parallel_rq(struct i915_request *rq)
-{
- return intel_context_is_parallel(rq->context);
-}
-
-static inline struct intel_context *request_to_parent(struct i915_request *rq)
-{
- return intel_context_to_parent(rq->context);
-}
-
static struct i915_request *
__i915_request_ensure_parallel_ordering(struct i915_request *rq,
struct intel_timeline *timeline)
--
2.32.0
next prev parent reply other threads:[~2021-10-04 22:12 UTC|newest]
Thread overview: 165+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-04 22:06 [PATCH 00/26] Parallel submission aka multi-bb execbuf Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 01/26] drm/i915/guc: Move GuC guc_id allocation under submission state sub-struct Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-07 3:06 ` John Harrison
2021-10-07 3:06 ` [Intel-gfx] " John Harrison
2021-10-07 15:05 ` Matthew Brost
2021-10-07 15:05 ` [Intel-gfx] " Matthew Brost
2021-10-07 18:13 ` John Harrison
2021-10-07 18:13 ` [Intel-gfx] " John Harrison
2021-10-04 22:06 ` [PATCH 02/26] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-07 3:37 ` John Harrison
2021-10-07 3:37 ` [Intel-gfx] " John Harrison
2021-10-08 1:28 ` Matthew Brost
2021-10-08 1:28 ` [Intel-gfx] " Matthew Brost
2021-10-08 18:23 ` Matthew Brost
2021-10-08 18:23 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 03/26] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost
2021-10-04 22:06 ` Matthew Brost
2021-10-07 3:45 ` John Harrison
2021-10-07 3:45 ` [Intel-gfx] " John Harrison
2021-10-07 15:19 ` Matthew Brost
2021-10-07 15:19 ` [Intel-gfx] " Matthew Brost
2021-10-07 18:15 ` John Harrison
2021-10-07 18:15 ` [Intel-gfx] " John Harrison
2021-10-08 1:23 ` Matthew Brost
2021-10-08 1:23 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 04/26] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-07 3:49 ` John Harrison
2021-10-07 3:49 ` [Intel-gfx] " John Harrison
2021-10-04 22:06 ` [Intel-gfx] [PATCH 05/26] drm/i915: Add logical engine mapping Matthew Brost
2021-10-04 22:06 ` Matthew Brost
2021-10-07 19:03 ` John Harrison
2021-10-07 19:03 ` [Intel-gfx] " John Harrison
2021-10-04 22:06 ` [PATCH 06/26] drm/i915: Expose logical engine instance to user Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 07/26] drm/i915/guc: Introduce context parent-child relationship Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-07 19:35 ` John Harrison
2021-10-07 19:35 ` [Intel-gfx] " John Harrison
2021-10-08 18:33 ` Matthew Brost
2021-10-08 18:33 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 08/26] drm/i915/guc: Add multi-lrc context registration Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-07 19:50 ` John Harrison
2021-10-07 19:50 ` [Intel-gfx] " John Harrison
2021-10-08 1:31 ` Matthew Brost
2021-10-08 1:31 ` [Intel-gfx] " Matthew Brost
2021-10-08 17:20 ` John Harrison
2021-10-08 17:29 ` Matthew Brost
2021-10-04 22:06 ` [PATCH 09/26] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-07 20:23 ` John Harrison
2021-10-07 20:23 ` [Intel-gfx] " John Harrison
2021-10-04 22:06 ` [PATCH 10/26] drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-07 22:03 ` John Harrison
2021-10-07 22:03 ` [Intel-gfx] " John Harrison
2021-10-08 1:21 ` Matthew Brost
2021-10-08 1:21 ` [Intel-gfx] " Matthew Brost
2021-10-08 16:40 ` John Harrison
2021-10-08 16:40 ` [Intel-gfx] " John Harrison
2021-10-13 18:03 ` Matthew Brost
2021-10-13 18:03 ` [Intel-gfx] " Matthew Brost
2021-10-13 19:11 ` John Harrison
2021-10-13 19:11 ` [Intel-gfx] " John Harrison
2021-10-04 22:06 ` [Intel-gfx] [PATCH 11/26] drm/i915/guc: Implement parallel context pin / unpin functions Matthew Brost
2021-10-04 22:06 ` Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 12/26] drm/i915/guc: Implement multi-lrc submission Matthew Brost
2021-10-04 22:06 ` Matthew Brost
2021-10-05 7:55 ` [Intel-gfx] " kernel test robot
2021-10-05 7:55 ` kernel test robot
2021-10-05 10:37 ` kernel test robot
2021-10-05 10:37 ` kernel test robot
2021-10-08 17:20 ` John Harrison
2021-10-08 17:20 ` [Intel-gfx] " John Harrison
2021-10-13 18:24 ` Matthew Brost
2021-10-13 18:24 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 13/26] drm/i915/guc: Insert submit fences between requests in parent-child relationship Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 14/26] drm/i915/guc: Implement multi-lrc reset Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-08 17:39 ` John Harrison
2021-10-08 17:39 ` [Intel-gfx] " John Harrison
2021-10-08 17:56 ` Matthew Brost
2021-10-08 17:56 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 15/26] drm/i915/guc: Update debugfs for GuC multi-lrc Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-08 17:46 ` John Harrison
2021-10-08 17:46 ` [Intel-gfx] " John Harrison
2021-10-04 22:06 ` [PATCH 16/26] drm/i915: Fix bug in user proto-context creation that leaked contexts Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-08 17:49 ` John Harrison
2021-10-08 17:49 ` [Intel-gfx] " John Harrison
2021-10-04 22:06 ` [PATCH 17/26] drm/i915/guc: Connect UAPI to GuC multi-lrc interface Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-11 22:09 ` John Harrison
2021-10-11 22:09 ` [Intel-gfx] " John Harrison
2021-10-11 22:59 ` Matthew Brost
2021-10-11 22:59 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 18/26] drm/i915/doc: Update parallel submit doc to point to i915_drm.h Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 19/26] drm/i915/guc: Add basic GuC multi-lrc selftest Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 20/26] drm/i915/guc: Implement no mid batch preemption for multi-lrc Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-11 23:32 ` John Harrison
2021-10-11 23:32 ` [Intel-gfx] " John Harrison
2021-10-13 1:52 ` Matthew Brost
2021-10-13 1:52 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 21/26] drm/i915: Multi-BB execbuf Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-05 8:31 ` kernel test robot
2021-10-05 8:31 ` kernel test robot
2021-10-05 17:02 ` Matthew Brost
2021-10-06 20:46 ` Matthew Brost
2021-10-12 21:22 ` John Harrison
2021-10-12 21:22 ` [Intel-gfx] " John Harrison
2021-10-13 0:37 ` Matthew Brost
2021-10-13 0:37 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 22/26] drm/i915/guc: Handle errors in multi-lrc requests Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-12 21:56 ` John Harrison
2021-10-12 21:56 ` [Intel-gfx] " John Harrison
2021-10-13 0:18 ` Matthew Brost
2021-10-13 0:18 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` Matthew Brost [this message]
2021-10-04 22:06 ` [Intel-gfx] [PATCH 23/26] drm/i915: Make request conflict tracking understand parallel submits Matthew Brost
2021-10-12 22:08 ` John Harrison
2021-10-12 22:08 ` [Intel-gfx] " John Harrison
2021-10-13 0:32 ` Matthew Brost
2021-10-13 0:32 ` [Intel-gfx] " Matthew Brost
2021-10-13 19:35 ` John Harrison
2021-10-13 19:35 ` [Intel-gfx] " John Harrison
2021-10-13 17:51 ` Matthew Brost
2021-10-13 17:51 ` [Intel-gfx] " Matthew Brost
2021-10-13 19:25 ` John Harrison
2021-10-13 19:25 ` [Intel-gfx] " John Harrison
2021-10-04 22:06 ` [PATCH 24/26] drm/i915: Update I915_GEM_BUSY IOCTL to understand composite fences Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-11 22:15 ` Daniele Ceraolo Spurio
2021-10-11 22:15 ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-10-12 7:53 ` Tvrtko Ursulin
2021-10-12 18:31 ` Matthew Brost
2021-10-04 22:06 ` [PATCH 25/26] drm/i915: Enable multi-bb execbuf Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:06 ` [PATCH 26/26] drm/i915/execlists: Weak parallel submission support for execlists Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] " Matthew Brost
2021-10-04 22:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Parallel submission aka multi-bb execbuf (rev4) Patchwork
2021-10-12 22:15 ` John Harrison
2021-10-13 0:15 ` Matthew Brost
2021-10-13 19:24 ` John Harrison
2021-10-04 22:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-04 22:26 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-10-12 22:15 ` John Harrison
2021-10-13 0:12 ` Matthew Brost
2021-10-04 22:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-05 1:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Parallel submission aka multi-bb execbuf (rev5) Patchwork
2021-10-05 1:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-05 1:54 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-10-05 2:21 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-12 18:11 ` [PATCH 02/26] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost
2021-10-12 18:11 ` [Intel-gfx] " Matthew Brost
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211004220637.14746-24-matthew.brost@intel.com \
--to=matthew.brost@intel.com \
--cc=daniele.ceraolospurio@intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=john.c.harrison@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.