From: Richard Fitzgerald <rf@opensource.cirrus.com>
To: <broonie@kernel.org>
Cc: <alsa-devel@alsa-project.org>, <linux-kernel@vger.kernel.org>,
<patches@opensource.cirrus.com>,
Richard Fitzgerald <rf@opensource.cirrus.com>
Subject: [PATCH 13/16] ASoC: cs42l42: Set correct SRC MCLK
Date: Fri, 15 Oct 2021 14:36:16 +0100 [thread overview]
Message-ID: <20211015133619.4698-14-rf@opensource.cirrus.com> (raw)
In-Reply-To: <20211015133619.4698-1-rf@opensource.cirrus.com>
According to the datasheet the SRC MCLK must be as near as possible to
(125 * sample rate). This means it should be ~6MHz for rates up to 48k
and ~12MHz for rates above that. As per datasheet table 4-21.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
---
sound/soc/codecs/cs42l42.c | 58 ++++++++++++++++++++++++++++++++--------------
sound/soc/codecs/cs42l42.h | 1 +
2 files changed, 42 insertions(+), 17 deletions(-)
diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c
index 54b4bc391ee9..05b8ae62b20d 100644
--- a/sound/soc/codecs/cs42l42.c
+++ b/sound/soc/codecs/cs42l42.c
@@ -668,22 +668,6 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
CS42L42_FSYNC_PULSE_WIDTH_MASK,
CS42L42_FRAC1_VAL(fsync - 1) <<
CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
- /* Set the sample rates (96k or lower) */
- snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
- CS42L42_FS_EN_MASK,
- (CS42L42_FS_EN_IASRC_96K |
- CS42L42_FS_EN_OASRC_96K) <<
- CS42L42_FS_EN_SHIFT);
- /* Set the input/output internal MCLK clock ~12 MHz */
- snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
- CS42L42_CLK_IASRC_SEL_MASK,
- CS42L42_CLK_IASRC_SEL_12 <<
- CS42L42_CLK_IASRC_SEL_SHIFT);
- snd_soc_component_update_bits(component,
- CS42L42_OUT_ASRC_CLK,
- CS42L42_CLK_OASRC_SEL_MASK,
- CS42L42_CLK_OASRC_SEL_12 <<
- CS42L42_CLK_OASRC_SEL_SHIFT);
if (pll_ratio_table[i].mclk_src_sel == 0) {
/* Pass the clock straight through */
snd_soc_component_update_bits(component,
@@ -746,6 +730,39 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
return -EINVAL;
}
+static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
+{
+ struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
+ unsigned int fs;
+
+ /* Don't reconfigure if there is an audio stream running */
+ if (cs42l42->stream_use)
+ return;
+
+ /* SRC MCLK must be as close as possible to 125 * sample rate */
+ if (sample_rate <= 48000)
+ fs = CS42L42_CLK_IASRC_SEL_6;
+ else
+ fs = CS42L42_CLK_IASRC_SEL_12;
+
+ /* Set the sample rates (96k or lower) */
+ snd_soc_component_update_bits(component,
+ CS42L42_FS_RATE_EN,
+ CS42L42_FS_EN_MASK,
+ (CS42L42_FS_EN_IASRC_96K |
+ CS42L42_FS_EN_OASRC_96K) <<
+ CS42L42_FS_EN_SHIFT);
+
+ snd_soc_component_update_bits(component,
+ CS42L42_IN_ASRC_CLK,
+ CS42L42_CLK_IASRC_SEL_MASK,
+ fs << CS42L42_CLK_IASRC_SEL_SHIFT);
+ snd_soc_component_update_bits(component,
+ CS42L42_OUT_ASRC_CLK,
+ CS42L42_CLK_OASRC_SEL_MASK,
+ fs << CS42L42_CLK_OASRC_SEL_SHIFT);
+}
+
static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
@@ -836,6 +853,7 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
unsigned int channels = params_channels(params);
unsigned int width = (params_width(params) / 8) - 1;
unsigned int val = 0;
+ int ret;
cs42l42->srate = params_rate(params);
cs42l42->bclk = snd_soc_params_to_bclk(params);
@@ -889,7 +907,13 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
break;
}
- return cs42l42_pll_config(component);
+ ret = cs42l42_pll_config(component);
+ if (ret)
+ return ret;
+
+ cs42l42_src_config(component, params_rate(params));
+
+ return 0;
}
static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
diff --git a/sound/soc/codecs/cs42l42.h b/sound/soc/codecs/cs42l42.h
index 024760300937..46074624d300 100644
--- a/sound/soc/codecs/cs42l42.h
+++ b/sound/soc/codecs/cs42l42.h
@@ -347,6 +347,7 @@
#define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A)
#define CS42L42_CLK_IASRC_SEL_SHIFT 0
#define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT)
+#define CS42L42_CLK_IASRC_SEL_6 0
#define CS42L42_CLK_IASRC_SEL_12 1
#define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B)
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: Richard Fitzgerald <rf@opensource.cirrus.com>
To: <broonie@kernel.org>
Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org,
Richard Fitzgerald <rf@opensource.cirrus.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH 13/16] ASoC: cs42l42: Set correct SRC MCLK
Date: Fri, 15 Oct 2021 14:36:16 +0100 [thread overview]
Message-ID: <20211015133619.4698-14-rf@opensource.cirrus.com> (raw)
In-Reply-To: <20211015133619.4698-1-rf@opensource.cirrus.com>
According to the datasheet the SRC MCLK must be as near as possible to
(125 * sample rate). This means it should be ~6MHz for rates up to 48k
and ~12MHz for rates above that. As per datasheet table 4-21.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
---
sound/soc/codecs/cs42l42.c | 58 ++++++++++++++++++++++++++++++++--------------
sound/soc/codecs/cs42l42.h | 1 +
2 files changed, 42 insertions(+), 17 deletions(-)
diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c
index 54b4bc391ee9..05b8ae62b20d 100644
--- a/sound/soc/codecs/cs42l42.c
+++ b/sound/soc/codecs/cs42l42.c
@@ -668,22 +668,6 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
CS42L42_FSYNC_PULSE_WIDTH_MASK,
CS42L42_FRAC1_VAL(fsync - 1) <<
CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
- /* Set the sample rates (96k or lower) */
- snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
- CS42L42_FS_EN_MASK,
- (CS42L42_FS_EN_IASRC_96K |
- CS42L42_FS_EN_OASRC_96K) <<
- CS42L42_FS_EN_SHIFT);
- /* Set the input/output internal MCLK clock ~12 MHz */
- snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
- CS42L42_CLK_IASRC_SEL_MASK,
- CS42L42_CLK_IASRC_SEL_12 <<
- CS42L42_CLK_IASRC_SEL_SHIFT);
- snd_soc_component_update_bits(component,
- CS42L42_OUT_ASRC_CLK,
- CS42L42_CLK_OASRC_SEL_MASK,
- CS42L42_CLK_OASRC_SEL_12 <<
- CS42L42_CLK_OASRC_SEL_SHIFT);
if (pll_ratio_table[i].mclk_src_sel == 0) {
/* Pass the clock straight through */
snd_soc_component_update_bits(component,
@@ -746,6 +730,39 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
return -EINVAL;
}
+static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
+{
+ struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
+ unsigned int fs;
+
+ /* Don't reconfigure if there is an audio stream running */
+ if (cs42l42->stream_use)
+ return;
+
+ /* SRC MCLK must be as close as possible to 125 * sample rate */
+ if (sample_rate <= 48000)
+ fs = CS42L42_CLK_IASRC_SEL_6;
+ else
+ fs = CS42L42_CLK_IASRC_SEL_12;
+
+ /* Set the sample rates (96k or lower) */
+ snd_soc_component_update_bits(component,
+ CS42L42_FS_RATE_EN,
+ CS42L42_FS_EN_MASK,
+ (CS42L42_FS_EN_IASRC_96K |
+ CS42L42_FS_EN_OASRC_96K) <<
+ CS42L42_FS_EN_SHIFT);
+
+ snd_soc_component_update_bits(component,
+ CS42L42_IN_ASRC_CLK,
+ CS42L42_CLK_IASRC_SEL_MASK,
+ fs << CS42L42_CLK_IASRC_SEL_SHIFT);
+ snd_soc_component_update_bits(component,
+ CS42L42_OUT_ASRC_CLK,
+ CS42L42_CLK_OASRC_SEL_MASK,
+ fs << CS42L42_CLK_OASRC_SEL_SHIFT);
+}
+
static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
@@ -836,6 +853,7 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
unsigned int channels = params_channels(params);
unsigned int width = (params_width(params) / 8) - 1;
unsigned int val = 0;
+ int ret;
cs42l42->srate = params_rate(params);
cs42l42->bclk = snd_soc_params_to_bclk(params);
@@ -889,7 +907,13 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
break;
}
- return cs42l42_pll_config(component);
+ ret = cs42l42_pll_config(component);
+ if (ret)
+ return ret;
+
+ cs42l42_src_config(component, params_rate(params));
+
+ return 0;
}
static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
diff --git a/sound/soc/codecs/cs42l42.h b/sound/soc/codecs/cs42l42.h
index 024760300937..46074624d300 100644
--- a/sound/soc/codecs/cs42l42.h
+++ b/sound/soc/codecs/cs42l42.h
@@ -347,6 +347,7 @@
#define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A)
#define CS42L42_CLK_IASRC_SEL_SHIFT 0
#define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT)
+#define CS42L42_CLK_IASRC_SEL_6 0
#define CS42L42_CLK_IASRC_SEL_12 1
#define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B)
--
2.11.0
next prev parent reply other threads:[~2021-10-15 13:37 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-15 13:36 [PATCH 00/16] ASoC: cs42l42: Collection of bugfixes Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 01/16] ASoC: cs42l42: Don't reconfigure the PLL while it is running Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 02/16] ASoC: cs42l42: Always configure both ASP TX channels Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 03/16] ASoC: cs42l42: Correct some register default values Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 04/16] ASoC: cs42l42: Don't set defaults for volatile registers Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 05/16] ASoC: cs42l42: Defer probe if request_threaded_irq() returns EPROBE_DEFER Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 06/16] ASoC: cs42l42: Reset GPIO is mandatory Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 14:30 ` Mark Brown
2021-10-15 14:30 ` Mark Brown
2021-10-15 13:36 ` [PATCH 07/16] ASoC: cs42l42: Correct power-up sequence to match datasheet Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 15:02 ` Mark Brown
2021-10-15 15:02 ` Mark Brown
2021-10-15 13:36 ` [PATCH 08/16] ASoC: cs42l42: Reset and power-down on driver remove() Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 15:04 ` Mark Brown
2021-10-15 15:04 ` Mark Brown
2021-10-15 13:36 ` [PATCH 09/16] ASoC: cs42l42: Prevent NULL pointer deref in interrupt handler Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 10/16] ASoC: cs42l42: Don't claim to support 192k Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 11/16] ASoC: cs42l42: Use PLL for SCLK > 12.288MHz Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 12/16] ASoC: cs42l42: Allow time for HP/ADC to power-up after enable Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald [this message]
2021-10-15 13:36 ` [PATCH 13/16] ASoC: cs42l42: Set correct SRC MCLK Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 14/16] ASoC: cs42l42: Mark OSC_SWITCH_STATUS register volatile Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 15/16] ASoC: cs42l42: Fix WARN in remove() if running without an interrupt Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 13:36 ` [PATCH 16/16] ASoC: cs42l42: Always enable TS_PLUG and TS_UNPLUG interrupts Richard Fitzgerald
2021-10-15 13:36 ` Richard Fitzgerald
2021-10-15 19:42 ` (subset) [PATCH 00/16] ASoC: cs42l42: Collection of bugfixes Mark Brown
2021-10-15 19:42 ` Mark Brown
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