All of lore.kernel.org
 help / color / mirror / Atom feed
From: Yazen Ghannam <yazen.ghannam@amd.com>
To: <linux-edac@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <bp@alien8.de>,
	<mchehab@kernel.org>, <tony.luck@intel.com>,
	<james.morse@arm.com>, <rric@kernel.org>,
	<Smita.KoralahalliChannabasappa@amd.com>,
	<NaveenKrishna.Chatradhi@amd.com>, <Muralidhara.MK@amd.com>,
	Yazen Ghannam <yazen.ghannam@amd.com>
Subject: [PATCH v3 06/33] EDAC/amd64: Define functions for DramOffset
Date: Thu, 28 Oct 2021 17:57:01 +0000	[thread overview]
Message-ID: <20211028175728.121452-7-yazen.ghannam@amd.com> (raw)
In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com>

Add helper functions to read the DramOffset register and to remove the
offset from the calculated address.

The helper functions will be expanded in future DF versions.

Rename the "base" variable to "map_num" to indicate that this is the
address map number. An address map is defined with a base and limit
value. The map_num variable is used to select the proper base and limit
registers to use for the address translation.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20210623192002.3671647-8-yazen.ghannam@amd.com

v2->v3:
* Was patch 7 in v2.
* Dropped "df_regs" use.

v1->v2:
* Moved from arch/x86 to EDAC.
* Add function to data_fabric_ops.

 drivers/edac/amd64_edac.c | 58 +++++++++++++++++++++++++++++----------
 1 file changed, 43 insertions(+), 15 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index f83f9813294d..d7780e570fd0 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1049,21 +1049,60 @@ static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo)
 	return __df_indirect_read(node, func, reg, DF_BROADCAST, lo);
 }
 
+/* Use "reg_" prefix for raw register values. */
 struct addr_ctx {
 	u64 ret_addr;
 	u32 tmp;
+	u32 reg_dram_offset;
 	u16 nid;
 	u8 inst_id;
+	u8 map_num;
 };
 
 struct data_fabric_ops {
+	u64	(*get_hi_addr_offset)		(struct addr_ctx *ctx);
 };
 
+static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx)
+{
+	return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8;
+}
+
 struct data_fabric_ops df2_ops = {
+	.get_hi_addr_offset		=	get_hi_addr_offset_df2,
 };
 
 struct data_fabric_ops *df_ops;
 
+static int get_dram_offset_reg(struct addr_ctx *ctx)
+{
+	/* Read D18F0x1B4 (DramOffset) */
+	if (df_indirect_read_instance(ctx->nid, 0, 0x1B4, ctx->inst_id, &ctx->reg_dram_offset))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int remove_dram_offset(struct addr_ctx *ctx)
+{
+	if (get_dram_offset_reg(ctx))
+		return -EINVAL;
+
+	ctx->map_num = 0;
+
+	/* Remove HiAddrOffset from normalized address, if enabled: */
+	if (ctx->reg_dram_offset & BIT(0)) {
+		u64 hi_addr_offset = df_ops->get_hi_addr_offset(ctx);
+
+		if (ctx->ret_addr >= hi_addr_offset) {
+			ctx->ret_addr -= hi_addr_offset;
+			ctx->map_num = 1;
+		}
+	}
+
+	return 0;
+}
+
 static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
 {
 	u64 dram_base_addr, dram_limit_addr, dram_hole_base;
@@ -1072,7 +1111,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 	u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
 	u8 intlv_addr_sel, intlv_addr_bit;
 	u8 num_intlv_bits, hashed_bit;
-	u8 lgcy_mmio_hole_en, base = 0;
+	u8 lgcy_mmio_hole_en;
 	u8 cs_mask, cs_id = 0;
 	bool hash_enabled = false;
 
@@ -1089,22 +1128,11 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 	ctx.nid = nid;
 	ctx.inst_id = umc;
 
-	/* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
-	if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp))
+	if (remove_dram_offset(&ctx))
 		goto out_err;
 
-	/* Remove HiAddrOffset from normalized address, if enabled: */
-	if (ctx.tmp & BIT(0)) {
-		u64 hi_addr_offset = (ctx.tmp & GENMASK_ULL(31, 20)) << 8;
-
-		if (norm_addr >= hi_addr_offset) {
-			ctx.ret_addr -= hi_addr_offset;
-			base = 1;
-		}
-	}
-
 	/* Read D18F0x110 (DramBaseAddress). */
-	if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &ctx.tmp))
+	if (df_indirect_read_instance(nid, 0, 0x110 + (8 * ctx.map_num), umc, &ctx.tmp))
 		goto out_err;
 
 	/* Check if address range is valid. */
@@ -1127,7 +1155,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 	}
 
 	/* Read D18F0x114 (DramLimitAddress). */
-	if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp))
+	if (df_indirect_read_instance(nid, 0, 0x114 + (8 * ctx.map_num), umc, &ctx.tmp))
 		goto out_err;
 
 	intlv_num_sockets = (ctx.tmp >> 8) & 0x1;
-- 
2.25.1


  parent reply	other threads:[~2021-10-28 17:58 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-28 17:56 [PATCH v3 00/33] AMD MCA Address Translation Updates Yazen Ghannam
2021-10-28 17:56 ` [PATCH v3 01/33] x86/MCE/AMD, EDAC/amd64: Move address translation to AMD64 EDAC Yazen Ghannam
2021-11-15 16:17   ` [tip: ras/core] " tip-bot2 for Yazen Ghannam
2021-10-28 17:56 ` [PATCH v3 02/33] x86/amd_nb, EDAC/amd64: Move DF Indirect Read " Yazen Ghannam
2021-11-15 16:17   ` [tip: ras/core] " tip-bot2 for Yazen Ghannam
2021-10-28 17:56 ` [PATCH v3 03/33] EDAC/amd64: Allow for DF Indirect Broadcast reads Yazen Ghannam
2021-11-15 16:17   ` [tip: ras/core] " tip-bot2 for Yazen Ghannam
2021-10-28 17:56 ` [PATCH v3 04/33] EDAC/amd64: Add context struct Yazen Ghannam
2021-11-15 16:17   ` [tip: ras/core] " tip-bot2 for Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 05/33] EDAC/amd64: Define Data Fabric operations Yazen Ghannam
2021-10-28 17:57 ` Yazen Ghannam [this message]
2021-10-28 17:57 ` [PATCH v3 07/33] EDAC/amd64: Define function to read DRAM address map registers Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 08/33] EDAC/amd64: Define function to find interleaving mode Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 09/33] EDAC/amd64: Define function to denormalize address Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 10/33] EDAC/amd64: Define function to add DRAM base and hole Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 11/33] EDAC/amd64: Define function to dehash address Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 12/33] EDAC/amd64: Define function to check DRAM limit address Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 13/33] EDAC/amd64: Remove goto statements Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 14/33] EDAC/amd64: Simplify function parameters Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 15/33] EDAC/amd64: Define function to get Interleave Address Bit Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 16/33] EDAC/amd64: Skip denormalization if no interleaving Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 17/33] EDAC/amd64: Define function to get number of interleaved channels Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 18/33] EDAC/amd64: Define function to get number of interleaved dies Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 19/33] EDAC/amd64: Define function to get number of interleaved sockets Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 20/33] EDAC/amd64: Remove unnecessary assert Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 21/33] EDAC/amd64: Define function to make space for CS ID Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 22/33] EDAC/amd64: Define function to calculate " Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 23/33] EDAC/amd64: Define function to insert CS ID into address Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 24/33] EDAC/amd64: Define function to get CS Fabric ID Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 25/33] EDAC/amd64: Define function to find shift and mask values Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 26/33] EDAC/amd64: Update CS ID calculation to match reference code Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 27/33] EDAC/amd64: Match hash function to " Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 28/33] EDAC/amd64: Define function to get interleave address select bit Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 29/33] EDAC/amd64: Add support for address translation on DF3 systems Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 30/33] EDAC/amd64: Add glossary of acronyms for address translation Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 31/33] EDAC/amd64: Add check for when to add DRAM base and hole Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 32/33] EDAC/amd64: Save the number of block instances Yazen Ghannam
2021-10-28 17:57 ` [PATCH v3 33/33] EDAC/amd64: Add address translation support for DF3.5 Yazen Ghannam

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211028175728.121452-7-yazen.ghannam@amd.com \
    --to=yazen.ghannam@amd.com \
    --cc=Muralidhara.MK@amd.com \
    --cc=NaveenKrishna.Chatradhi@amd.com \
    --cc=Smita.KoralahalliChannabasappa@amd.com \
    --cc=bp@alien8.de \
    --cc=james.morse@arm.com \
    --cc=linux-edac@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mchehab@kernel.org \
    --cc=rric@kernel.org \
    --cc=tony.luck@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.