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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 01/17] drm/i915/fbc: Exract snb_fbc_program_fence()
Date: Thu,  4 Nov 2021 16:45:04 +0200	[thread overview]
Message-ID: <20211104144520.22605-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have two identical copies of the snb+ system agent
CPU fence programming code. Extract into a helper.

Also there's no real point in insisting that we
program 0 into DPFC_CPU_FENCE_OFFSET when the fence is
disabled. So just always stick the computed Y offset there
whether or not the fence is actually used or not.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 39 ++++++++++++------------
 1 file changed, 19 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 834eb4cc7c10..6bd952a37901 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -307,6 +307,18 @@ static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 		i8xx_fbc_recompress(dev_priv);
 }
 
+static void snb_fbc_program_fence(struct drm_i915_private *i915)
+{
+	const struct intel_fbc_reg_params *params = &i915->fbc.params;
+	u32 ctl = 0;
+
+	if (params->fence_id >= 0)
+		ctl = SNB_CPU_FENCE_ENABLE | params->fence_id;
+
+	intel_de_write(i915, SNB_DPFC_CTL_SA, ctl);
+	intel_de_write(i915, DPFC_CPU_FENCE_OFFSET, params->fence_y_offset);
+}
+
 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 {
 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
@@ -320,19 +332,11 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 		dpfc_ctl |= DPFC_CTL_FENCE_EN;
 		if (IS_IRONLAKE(dev_priv))
 			dpfc_ctl |= params->fence_id;
-		if (IS_SANDYBRIDGE(dev_priv)) {
-			intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
-				       SNB_CPU_FENCE_ENABLE | params->fence_id);
-			intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
-				       params->fence_y_offset);
-		}
-	} else {
-		if (IS_SANDYBRIDGE(dev_priv)) {
-			intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
-			intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
-		}
 	}
 
+	if (IS_SANDYBRIDGE(dev_priv))
+		snb_fbc_program_fence(dev_priv);
+
 	intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF,
 		       params->fence_y_offset);
 	/* enable it... */
@@ -389,20 +393,15 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 
 	dpfc_ctl |= g4x_dpfc_ctl_limit(dev_priv);
 
-	if (params->fence_id >= 0) {
+	if (params->fence_id >= 0)
 		dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
-		intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
-			       SNB_CPU_FENCE_ENABLE | params->fence_id);
-		intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
-			       params->fence_y_offset);
-	} else if (dev_priv->ggtt.num_fences) {
-		intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
-		intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
-	}
 
 	if (dev_priv->fbc.false_color)
 		dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 
+	if (dev_priv->ggtt.num_fences)
+		snb_fbc_program_fence(dev_priv);
+
 	intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 }
 
-- 
2.32.0


  reply	other threads:[~2021-11-04 14:45 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-04 14:45 [Intel-gfx] [PATCH 00/17] drm/i915/fbc: Prep work for multiple FBC instances Ville Syrjala
2021-11-04 14:45 ` Ville Syrjala [this message]
2021-11-04 14:45 ` [Intel-gfx] [PATCH 02/17] drm/i915/fbc: Extract {skl, glk}_fbc_program_cfb_stride() Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 03/17] drm/i915/fbc: Just use params->fence_y_offset always Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 04/17] drm/i915/fbc: Introduce intel_fbc_is_compressing() Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 05/17] drm/i915/fbc: Extract helpers to compute FBC control register values Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 06/17] drm/i915/fbc: Introduce intel_fbc_funcs Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 07/17] drm/i915/fbc: Introduce .nuke() vfunc Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 08/17] drm/i915/fbc: s/gen7/ivb/ Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 09/17] drm/i915/fbc: Introduce .program_cfb() vfunc Ville Syrjala
2021-11-12 11:11   ` Jani Nikula
2021-11-04 14:45 ` [Intel-gfx] [PATCH 10/17] drm/i915/fbc: Introduce intel_fbc_set_false_color() Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 11/17] drm/i915/fbc: Nuke BDW_FBC_COMP_SEG_MASK Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 12/17] drm/i915/fbc: Clean up all register defines Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 13/17] drm/i915/fbc: Finish polishing FBC1 registers Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 14/17] drm/i915: Relocate FBC_LLC_READ_CTRL Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 15/17] drm/i915/fbc: s/dev_priv/i915/ Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 16/17] drm/i915/fbc: Start passing around intel_fbc Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 17/17] drm/1915/fbc: Replace plane->has_fbc with a pointer to the fbc instance Ville Syrjala
2021-11-04 18:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: Prep work for multiple FBC instances Patchwork
2021-11-04 18:52 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-11-04 19:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-11-04 22:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-11-05 13:08 ` [Intel-gfx] [PATCH 00/17] " Jani Nikula
2021-11-11 12:28   ` Kahola, Mika

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