From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 07/17] drm/i915/fbc: Introduce .nuke() vfunc
Date: Thu, 4 Nov 2021 16:45:10 +0200 [thread overview]
Message-ID: <20211104144520.22605-8-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Eliminate yet another if-ladder by adding .nuke() vfunc.
We also rename all *_recompress() stuff to *_nuke() since
that's the terminology the spec uses. Also "recompress"
is a bit confusing by perhaps implying that this triggers
an immediate recompression. Depending on the hardware that
may definitely not be the case, and in general we don't
specifically know when the hardware decides to compress.
So all we do is "nuke" the current compressed framebuffer
and leave it up to the hardware to recompress later if it
so chooses.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 145 +++++++++++++----------
1 file changed, 84 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index a2e09b6d21c7..be89404840d2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -53,6 +53,7 @@ struct intel_fbc_funcs {
void (*deactivate)(struct drm_i915_private *i915);
bool (*is_active)(struct drm_i915_private *i915);
bool (*is_compressing)(struct drm_i915_private *i915);
+ void (*nuke)(struct drm_i915_private *i915);
};
/*
@@ -243,11 +244,42 @@ static bool i8xx_fbc_is_compressing(struct drm_i915_private *i915)
(FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED);
}
+static void i8xx_fbc_nuke(struct drm_i915_private *dev_priv)
+{
+ struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
+
+ spin_lock_irq(&dev_priv->uncore.lock);
+ intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
+ intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
+ spin_unlock_irq(&dev_priv->uncore.lock);
+}
+
static const struct intel_fbc_funcs i8xx_fbc_funcs = {
.activate = i8xx_fbc_activate,
.deactivate = i8xx_fbc_deactivate,
.is_active = i8xx_fbc_is_active,
.is_compressing = i8xx_fbc_is_compressing,
+ .nuke = i8xx_fbc_nuke,
+};
+
+static void i965_fbc_nuke(struct drm_i915_private *dev_priv)
+{
+ struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
+
+ spin_lock_irq(&dev_priv->uncore.lock);
+ intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
+ intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
+ spin_unlock_irq(&dev_priv->uncore.lock);
+}
+
+static const struct intel_fbc_funcs i965_fbc_funcs = {
+ .activate = i8xx_fbc_activate,
+ .deactivate = i8xx_fbc_deactivate,
+ .is_active = i8xx_fbc_is_active,
+ .is_compressing = i8xx_fbc_is_compressing,
+ .nuke = i965_fbc_nuke,
};
static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915)
@@ -324,70 +356,13 @@ static const struct intel_fbc_funcs g4x_fbc_funcs = {
.deactivate = g4x_fbc_deactivate,
.is_active = g4x_fbc_is_active,
.is_compressing = g4x_fbc_is_compressing,
+ .nuke = i965_fbc_nuke,
};
-static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
-{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
- enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
-
- spin_lock_irq(&dev_priv->uncore.lock);
- intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
- intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
- spin_unlock_irq(&dev_priv->uncore.lock);
-}
-
-static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
-{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
- enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
-
- spin_lock_irq(&dev_priv->uncore.lock);
- intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
- intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
- spin_unlock_irq(&dev_priv->uncore.lock);
-}
-
-/* This function forces a CFB recompression through the nuke operation. */
-static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
-{
- intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE);
- intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
-}
-
-static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
-{
- struct intel_fbc *fbc = &dev_priv->fbc;
-
- trace_intel_fbc_nuke(fbc->crtc);
-
- if (DISPLAY_VER(dev_priv) >= 6)
- snb_fbc_recompress(dev_priv);
- else if (DISPLAY_VER(dev_priv) >= 4)
- i965_fbc_recompress(dev_priv);
- else
- i8xx_fbc_recompress(dev_priv);
-}
-
-static void snb_fbc_program_fence(struct drm_i915_private *i915)
-{
- const struct intel_fbc_reg_params *params = &i915->fbc.params;
- u32 ctl = 0;
-
- if (params->fence_id >= 0)
- ctl = SNB_CPU_FENCE_ENABLE | params->fence_id;
-
- intel_de_write(i915, SNB_DPFC_CTL_SA, ctl);
- intel_de_write(i915, DPFC_CPU_FENCE_OFFSET, params->fence_y_offset);
-}
-
static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
{
struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
- if (IS_SANDYBRIDGE(dev_priv))
- snb_fbc_program_fence(dev_priv);
-
intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF,
params->fence_y_offset);
@@ -422,6 +397,40 @@ static const struct intel_fbc_funcs ilk_fbc_funcs = {
.deactivate = ilk_fbc_deactivate,
.is_active = ilk_fbc_is_active,
.is_compressing = ilk_fbc_is_compressing,
+ .nuke = i965_fbc_nuke,
+};
+
+static void snb_fbc_program_fence(struct drm_i915_private *i915)
+{
+ const struct intel_fbc_reg_params *params = &i915->fbc.params;
+ u32 ctl = 0;
+
+ if (params->fence_id >= 0)
+ ctl = SNB_CPU_FENCE_ENABLE | params->fence_id;
+
+ intel_de_write(i915, SNB_DPFC_CTL_SA, ctl);
+ intel_de_write(i915, DPFC_CPU_FENCE_OFFSET, params->fence_y_offset);
+}
+
+static void snb_fbc_activate(struct drm_i915_private *dev_priv)
+{
+ snb_fbc_program_fence(dev_priv);
+
+ ilk_fbc_activate(dev_priv);
+}
+
+static void snb_fbc_nuke(struct drm_i915_private *dev_priv)
+{
+ intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE);
+ intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
+}
+
+static const struct intel_fbc_funcs snb_fbc_funcs = {
+ .activate = snb_fbc_activate,
+ .deactivate = ilk_fbc_deactivate,
+ .is_active = ilk_fbc_is_active,
+ .is_compressing = ilk_fbc_is_compressing,
+ .nuke = snb_fbc_nuke,
};
static void glk_fbc_program_cfb_stride(struct drm_i915_private *i915)
@@ -499,6 +508,7 @@ static const struct intel_fbc_funcs gen7_fbc_funcs = {
.deactivate = ilk_fbc_deactivate,
.is_active = ilk_fbc_is_active,
.is_compressing = gen7_fbc_is_compressing,
+ .nuke = snb_fbc_nuke,
};
static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
@@ -538,6 +548,15 @@ bool intel_fbc_is_compressing(struct drm_i915_private *i915)
return fbc->funcs->is_compressing(i915);
}
+static void intel_fbc_nuke(struct drm_i915_private *i915)
+{
+ struct intel_fbc *fbc = &i915->fbc;
+
+ trace_intel_fbc_nuke(fbc->crtc);
+
+ fbc->funcs->nuke(i915);
+}
+
/**
* intel_fbc_is_active - Is FBC active?
* @dev_priv: i915 device instance
@@ -555,7 +574,7 @@ bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
static void intel_fbc_activate(struct drm_i915_private *dev_priv)
{
intel_fbc_hw_activate(dev_priv);
- intel_fbc_recompress(dev_priv);
+ intel_fbc_nuke(dev_priv);
}
static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
@@ -1318,7 +1337,7 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
if (!fbc->busy_bits && fbc->crtc &&
(frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
if (fbc->active)
- intel_fbc_recompress(dev_priv);
+ intel_fbc_nuke(dev_priv);
else if (!fbc->flip_pending)
__intel_fbc_post_update(fbc->crtc);
}
@@ -1667,10 +1686,14 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
if (DISPLAY_VER(dev_priv) >= 7)
fbc->funcs = &gen7_fbc_funcs;
- else if (DISPLAY_VER(dev_priv) >= 5)
+ else if (DISPLAY_VER(dev_priv) == 6)
+ fbc->funcs = &snb_fbc_funcs;
+ else if (DISPLAY_VER(dev_priv) == 5)
fbc->funcs = &ilk_fbc_funcs;
else if (IS_G4X(dev_priv))
fbc->funcs = &g4x_fbc_funcs;
+ else if (DISPLAY_VER(dev_priv) == 4)
+ fbc->funcs = &i965_fbc_funcs;
else
fbc->funcs = &i8xx_fbc_funcs;
--
2.32.0
next prev parent reply other threads:[~2021-11-04 14:45 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-04 14:45 [Intel-gfx] [PATCH 00/17] drm/i915/fbc: Prep work for multiple FBC instances Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 01/17] drm/i915/fbc: Exract snb_fbc_program_fence() Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 02/17] drm/i915/fbc: Extract {skl, glk}_fbc_program_cfb_stride() Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 03/17] drm/i915/fbc: Just use params->fence_y_offset always Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 04/17] drm/i915/fbc: Introduce intel_fbc_is_compressing() Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 05/17] drm/i915/fbc: Extract helpers to compute FBC control register values Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 06/17] drm/i915/fbc: Introduce intel_fbc_funcs Ville Syrjala
2021-11-04 14:45 ` Ville Syrjala [this message]
2021-11-04 14:45 ` [Intel-gfx] [PATCH 08/17] drm/i915/fbc: s/gen7/ivb/ Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 09/17] drm/i915/fbc: Introduce .program_cfb() vfunc Ville Syrjala
2021-11-12 11:11 ` Jani Nikula
2021-11-04 14:45 ` [Intel-gfx] [PATCH 10/17] drm/i915/fbc: Introduce intel_fbc_set_false_color() Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 11/17] drm/i915/fbc: Nuke BDW_FBC_COMP_SEG_MASK Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 12/17] drm/i915/fbc: Clean up all register defines Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 13/17] drm/i915/fbc: Finish polishing FBC1 registers Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 14/17] drm/i915: Relocate FBC_LLC_READ_CTRL Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 15/17] drm/i915/fbc: s/dev_priv/i915/ Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 16/17] drm/i915/fbc: Start passing around intel_fbc Ville Syrjala
2021-11-04 14:45 ` [Intel-gfx] [PATCH 17/17] drm/1915/fbc: Replace plane->has_fbc with a pointer to the fbc instance Ville Syrjala
2021-11-04 18:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: Prep work for multiple FBC instances Patchwork
2021-11-04 18:52 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-11-04 19:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-11-04 22:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-11-05 13:08 ` [Intel-gfx] [PATCH 00/17] " Jani Nikula
2021-11-11 12:28 ` Kahola, Mika
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211104144520.22605-8-ville.syrjala@linux.intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.