From: Florian Fainelli <f.fainelli@gmail.com> To: devicetree@vger.kernel.org Cc: "Florian Fainelli" <f.fainelli@gmail.com>, "Damien Le Moal" <damien.lemoal@opensource.wdc.com>, "Rob Herring" <robh+dt@kernel.org>, "Linus Walleij" <linus.walleij@linaro.org>, "Bartosz Golaszewski" <brgl@bgdev.pl>, bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), "Gregory Fong" <gregory.0xf0@gmail.com>, "Thomas Gleixner" <tglx@linutronix.de>, "Marc Zyngier" <maz@kernel.org>, "Ulf Hansson" <ulf.hansson@linaro.org>, "Thierry Reding" <thierry.reding@gmail.com>, "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>, "Lee Jones" <lee.jones@linaro.org>, "Philipp Zabel" <p.zabel@pengutronix.de>, "Matt Mackall" <mpm@selenic.com>, "Herbert Xu" <herbert@gondor.apana.org.au>, "Ray Jui" <rjui@broadcom.com>, "Scott Branden" <sbranden@broadcom.com>, "Alessandro Zummo" <a.zummo@towertech.it>, "Alexandre Belloni" <alexandre.belloni@bootlin.com>, "Rafael J. Wysocki" <rafael@kernel.org>, "Daniel Lezcano" <daniel.lezcano@linaro.org>, "Amit Kucheria" <amitk@kernel.org>, "Zhang Rui" <rui.zhang@intel.com>, "Markus Mayer" <mmayer@broadcom.com>, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "Al Cooper" <alcooperx@gmail.com>, "Doug Berger" <opendmb@gmail.com>, linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), linux-kernel@vger.kernel.org (open list), linux-gpio@vger.kernel.org (open list:GPIO SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-mmc@vger.kernel.org (open list:MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) AND...), linux-pwm@vger.kernel.org (open list:PWM SUBSYSTEM), linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR CORE), linux-rtc@vger.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM), linux-pm@vger.kernel.org (open list:THERMAL), linux-usb@vger.kernel.org (open list:USB SUBSYSTEM) Subject: [PATCH 13/14] dt-bindings: bus: Convert GISB arbiter to YAML Date: Wed, 1 Dec 2021 12:51:09 -0800 [thread overview] Message-ID: <20211201205110.41656-14-f.fainelli@gmail.com> (raw) In-Reply-To: <20211201205110.41656-1-f.fainelli@gmail.com> Convert the Broadcom STB GISB bus arbiter to YAML to help with validation. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- .../devicetree/bindings/bus/brcm,gisb-arb.txt | 34 ---------- .../bindings/bus/brcm,gisb-arb.yaml | 66 +++++++++++++++++++ 2 files changed, 66 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt create mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt deleted file mode 100644 index 10f6d0a8159d..000000000000 --- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt +++ /dev/null @@ -1,34 +0,0 @@ -Broadcom GISB bus Arbiter controller - -Required properties: - -- compatible: - "brcm,bcm7278-gisb-arb" for V7 28nm chips - "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips - "brcm,bcm7435-gisb-arb" for newer 40nm chips - "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips - "brcm,bcm7038-gisb-arb" for 130nm chips -- reg: specifies the base physical address and size of the registers -- interrupts: specifies the two interrupts (timeout and TEA) to be used from - the parent interrupt controller. A third optional interrupt may be specified - for breakpoints. - -Optional properties: - -- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB - masters are valid at the system level -- brcm,gisb-arb-master-names: string list of the litteral name of the GISB - masters. Should match the number of bits set in brcm,gisb-master-mask and - the order in which they appear - -Example: - -gisb-arb@f0400000 { - compatible = "brcm,gisb-arb"; - reg = <0xf0400000 0x800>; - interrupts = <0>, <2>; - interrupt-parent = <&sun_l2_intc>; - - brcm,gisb-arb-master-mask = <0x7>; - brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; -}; diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml new file mode 100644 index 000000000000..483b019275cd --- /dev/null +++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom GISB bus Arbiter controller + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - brcm,bcm7445-gisb-arb + - const: brcm,gisb-arb + - items: + - const: brcm,bcm7278-gisb-arb + - items: + - const: brcm,bcm7435-gisb-arb + - items: + - const: brcm,bcm7400-gisb-arb + - items: + - const: brcm,bcm7038-gisb-arb + - items: + - const: brcm,gisb-arb + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 3 + + brcm,gisb-arb-master-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + 32-bits wide bitmask used to specify which GISB masters are valid at the + system level + + brcm,gisb-arb-master-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: > + String list of the litteral name of the GISB masters. Should match the + number of bits set in brcm,gisb-master-mask and the order in which they + appear + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + gisb-arb@f0400000 { + compatible = "brcm,gisb-arb"; + reg = <0xf0400000 0x800>; + interrupts = <0>, <2>; + interrupt-parent = <&sun_l2_intc>; + brcm,gisb-arb-master-mask = <0x7>; + brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; + }; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Florian Fainelli <f.fainelli@gmail.com> To: devicetree@vger.kernel.org Cc: "Florian Fainelli" <f.fainelli@gmail.com>, "Damien Le Moal" <damien.lemoal@opensource.wdc.com>, "Rob Herring" <robh+dt@kernel.org>, "Linus Walleij" <linus.walleij@linaro.org>, "Bartosz Golaszewski" <brgl@bgdev.pl>, bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), "Gregory Fong" <gregory.0xf0@gmail.com>, "Thomas Gleixner" <tglx@linutronix.de>, "Marc Zyngier" <maz@kernel.org>, "Ulf Hansson" <ulf.hansson@linaro.org>, "Thierry Reding" <thierry.reding@gmail.com>, "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>, "Lee Jones" <lee.jones@linaro.org>, "Philipp Zabel" <p.zabel@pengutronix.de>, "Matt Mackall" <mpm@selenic.com>, "Herbert Xu" <herbert@gondor.apana.org.au>, "Ray Jui" <rjui@broadcom.com>, "Scott Branden" <sbranden@broadcom.com>, "Alessandro Zummo" <a.zummo@towertech.it>, "Alexandre Belloni" <alexandre.belloni@bootlin.com>, "Rafael J. Wysocki" <rafael@kernel.org>, "Daniel Lezcano" <daniel.lezcano@linaro.org>, "Amit Kucheria" <amitk@kernel.org>, "Zhang Rui" <rui.zhang@intel.com>, "Markus Mayer" <mmayer@broadcom.com>, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "Al Cooper" <alcooperx@gmail.com>, "Doug Berger" <opendmb@gmail.com>, linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), linux-kernel@vger.kernel.org (open list), linux-gpio@vger.kernel.org (open list:GPIO SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-mmc@vger.kernel.org (open list:MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) AND...), linux-pwm@vger.kernel.org (open list:PWM SUBSYSTEM), linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR CORE), linux-rtc@vger.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM), linux-pm@vger.kernel.org (open list:THERMAL), linux-usb@vger.kernel.org (open list:USB SUBSYSTEM) Subject: [PATCH 13/14] dt-bindings: bus: Convert GISB arbiter to YAML Date: Wed, 1 Dec 2021 12:51:09 -0800 [thread overview] Message-ID: <20211201205110.41656-14-f.fainelli@gmail.com> (raw) In-Reply-To: <20211201205110.41656-1-f.fainelli@gmail.com> Convert the Broadcom STB GISB bus arbiter to YAML to help with validation. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- .../devicetree/bindings/bus/brcm,gisb-arb.txt | 34 ---------- .../bindings/bus/brcm,gisb-arb.yaml | 66 +++++++++++++++++++ 2 files changed, 66 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt create mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt deleted file mode 100644 index 10f6d0a8159d..000000000000 --- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt +++ /dev/null @@ -1,34 +0,0 @@ -Broadcom GISB bus Arbiter controller - -Required properties: - -- compatible: - "brcm,bcm7278-gisb-arb" for V7 28nm chips - "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips - "brcm,bcm7435-gisb-arb" for newer 40nm chips - "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips - "brcm,bcm7038-gisb-arb" for 130nm chips -- reg: specifies the base physical address and size of the registers -- interrupts: specifies the two interrupts (timeout and TEA) to be used from - the parent interrupt controller. A third optional interrupt may be specified - for breakpoints. - -Optional properties: - -- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB - masters are valid at the system level -- brcm,gisb-arb-master-names: string list of the litteral name of the GISB - masters. Should match the number of bits set in brcm,gisb-master-mask and - the order in which they appear - -Example: - -gisb-arb@f0400000 { - compatible = "brcm,gisb-arb"; - reg = <0xf0400000 0x800>; - interrupts = <0>, <2>; - interrupt-parent = <&sun_l2_intc>; - - brcm,gisb-arb-master-mask = <0x7>; - brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; -}; diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml new file mode 100644 index 000000000000..483b019275cd --- /dev/null +++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom GISB bus Arbiter controller + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - brcm,bcm7445-gisb-arb + - const: brcm,gisb-arb + - items: + - const: brcm,bcm7278-gisb-arb + - items: + - const: brcm,bcm7435-gisb-arb + - items: + - const: brcm,bcm7400-gisb-arb + - items: + - const: brcm,bcm7038-gisb-arb + - items: + - const: brcm,gisb-arb + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 3 + + brcm,gisb-arb-master-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + 32-bits wide bitmask used to specify which GISB masters are valid at the + system level + + brcm,gisb-arb-master-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: > + String list of the litteral name of the GISB masters. Should match the + number of bits set in brcm,gisb-master-mask and the order in which they + appear + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + gisb-arb@f0400000 { + compatible = "brcm,gisb-arb"; + reg = <0xf0400000 0x800>; + interrupts = <0>, <2>; + interrupt-parent = <&sun_l2_intc>; + brcm,gisb-arb-master-mask = <0x7>; + brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; + }; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-12-01 20:53 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-01 20:50 [PATCH 00/14] Broadcom DT bindings updates to YAML Florian Fainelli 2021-12-01 20:50 ` Florian Fainelli 2021-12-01 20:50 ` [PATCH 01/14] dt-bindings: mmc: Convert Broadcom STB SDHCI binding " Florian Fainelli 2021-12-01 20:50 ` Florian Fainelli 2021-12-01 20:50 ` [PATCH 02/14] dt-bindings: reset: Convert Broadcom STB reset " Florian Fainelli 2021-12-01 20:50 ` Florian Fainelli 2021-12-01 20:50 ` [PATCH 03/14] dt-bindings: pwm: Convert BCM7038 PWM binding " Florian Fainelli 2021-12-01 20:50 ` Florian Fainelli 2021-12-01 20:51 ` [PATCH 04/14] dt-bindings: rtc: Convert Broadcom STB waketimer " Florian Fainelli 2021-12-01 20:51 ` Florian Fainelli 2021-12-01 20:51 ` [PATCH 05/14] dt-bindings: gpio: Convert Broadcom STB GPIO " Florian Fainelli 2021-12-01 20:51 ` Florian Fainelli 2021-12-02 16:00 ` Gregory Fong 2021-12-02 16:00 ` Gregory Fong 2021-12-02 21:24 ` Florian Fainelli 2021-12-02 21:24 ` Florian Fainelli 2021-12-01 20:51 ` [PATCH 06/14] dt-binding: interrupt-controller: Convert BCM7038 L1 intc " Florian Fainelli 2021-12-01 20:51 ` Florian Fainelli 2021-12-01 20:51 ` [PATCH 07/14] dt-bindings: interrupt-controller: Convert BCM7120 L2 " Florian Fainelli 2021-12-01 20:51 ` Florian Fainelli 2021-12-01 20:51 ` [PATCH 08/14] dt-bindings: interrupt-controller: Merge BCM3380 with BCM7120 Florian Fainelli 2021-12-01 20:51 ` Florian Fainelli 2021-12-01 20:51 ` [PATCH 09/14] dt-bindings: interrupt-controller: Convert Broadcom STB L2 to YAML Florian Fainelli 2021-12-01 20:51 ` Florian Fainelli 2021-12-01 20:51 ` [PATCH 10/14] dt-bindings: rng: Convert iProc RNG200 " Florian Fainelli 2021-12-01 20:51 ` Florian Fainelli 2021-12-01 20:51 ` [PATCH 11/14] dt-bindings: thermal: Convert Broadcom TMON " Florian Fainelli 2021-12-01 20:51 ` Florian Fainelli 2021-12-01 20:51 ` [PATCH 12/14] dt-bindings: ata: Convert Broadcom SATA " Florian Fainelli 2021-12-01 20:51 ` Florian Fainelli 2021-12-01 23:58 ` Damien Le Moal 2021-12-01 23:58 ` Damien Le Moal 2021-12-01 20:51 ` Florian Fainelli [this message] 2021-12-01 20:51 ` [PATCH 13/14] dt-bindings: bus: Convert GISB arbiter " Florian Fainelli 2021-12-01 20:51 ` [PATCH 14/14] dt-bindings: usb: Convert BDC " Florian Fainelli 2021-12-01 20:51 ` Florian Fainelli
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