From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 02/24] serial: sh-sci: Add support for RZ/G2L SoC
Date: Thu, 16 Dec 2021 12:54:24 +0000 [thread overview]
Message-ID: <20211216125446.15451-3-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20211216125446.15451-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 3b2cd60689fa439481f535ee4463fb223a276f43 upstream.
Add serial support for RZ/G2L SoC with earlycon and
extended mode register support.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210603221758.10305-11-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/tty/serial/sh-sci.c | 12 +++++++++++-
drivers/tty/serial/sh-sci.h | 1 +
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index f700bfaef129..c3fd49480ad3 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -289,7 +289,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
},
/*
- * The "SCIFA" that is in RZ/T and RZ/A2.
+ * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
* It looks like a normal SCIF with FIFO data, but with a
* compressed address space. Also, the break out of interrupts
* are different: ERI/BRI, RXI, TXI, TEI, DRI.
@@ -306,6 +306,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
[SCFDR] = { 0x0E, 16 },
[SCSPTR] = { 0x10, 16 },
[SCLSR] = { 0x12, 16 },
+ [SEMR] = { 0x14, 8 },
},
.fifosize = 16,
.overrun_reg = SCLSR,
@@ -2527,6 +2528,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
if (termios->c_cflag & PARENB)
bits++;
+ if (sci_getreg(port, SEMR)->size)
+ serial_port_out(port, SEMR, 0);
+
if (best_clk >= 0) {
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
switch (srr + 1) {
@@ -3194,6 +3198,10 @@ static const struct of_device_id of_sci_match[] = {
.compatible = "renesas,scif-r7s9210",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
},
+ {
+ .compatible = "renesas,scif-r9a07g044",
+ .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
+ },
/* Family-specific types */
{
.compatible = "renesas,rcar-gen1-scif",
@@ -3476,6 +3484,7 @@ static int __init rzscifa_early_console_setup(struct earlycon_device *device,
port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
return early_console_setup(device, PORT_SCIF);
}
+
static int __init scifa_early_console_setup(struct earlycon_device *device,
const char *opt)
{
@@ -3495,6 +3504,7 @@ static int __init hscif_early_console_setup(struct earlycon_device *device,
OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index c0dfe4382898..c0ae78632dda 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -31,6 +31,7 @@ enum {
SCCKS, /* BRG Clock Select Register */
HSRTRGR, /* Rx FIFO Data Count Trigger Register */
HSTTRGR, /* Tx FIFO Data Count Trigger Register */
+ SEMR, /* Serial extended mode register */
SCIx_NR_REGS,
};
--
2.17.1
next prev parent reply other threads:[~2021-12-16 12:54 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 12:54 [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 01/24] dt-bindings: serial: renesas,scif: Document r9a07g044 bindings Lad Prabhakar
2021-12-16 12:54 ` Lad Prabhakar [this message]
2021-12-16 12:54 ` [PATCH 5.10.y-cip 03/24] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 04/24] dt-bindings: clock: Add r9a07g044 CPG Clock Definitions Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 05/24] clk: renesas: Add CPG core wrapper for RZ/G2L SoC Lad Prabhakar
2021-12-17 10:10 ` Pavel Machek
2021-12-17 11:03 ` Prabhakar Mahadev Lad
2021-12-16 12:54 ` [PATCH 5.10.y-cip 06/24] clk: renesas: Add support for R9A07G044 SoC Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 07/24] clk: renesas: r9a07g044: Rename divider table Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 08/24] clk: renesas: r9a07g044: Fix P1 Clock Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 09/24] clk: renesas: r9a07g044: Add P2 Clock support Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l: Add multi clock PM support Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 11/24] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Lad Prabhakar
2021-12-17 10:19 ` Pavel Machek
2021-12-17 11:11 ` Prabhakar Mahadev Lad
2021-12-16 12:54 ` [PATCH 5.10.y-cip 12/24] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 13/24] arm64: dts: renesas: r9a07g044: Add SYSC node Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 14/24] dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 15/24] clk: renesas: rzg2l: Remove unneeded semicolon Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 16/24] clk: renesas: rzg2l: Fix return value and unused assignment Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 17/24] clk: renesas: rzg2l: Fix a double free on error Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 18/24] clk: renesas: rzg2l: Avoid mixing error pointers and NULL Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 19/24] clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 20/24] clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 21/24] clk: mux: provide devm_clk_hw_register_mux() Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 22/24] clk: renesas: rzg2l: Add support to handle MUX clocks Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 23/24] clk: renesas: rzg2l: Add support to handle coupled clocks Lad Prabhakar
2021-12-17 10:38 ` Pavel Machek
2021-12-17 11:29 ` Prabhakar Mahadev Lad
2021-12-16 12:54 ` [PATCH 5.10.y-cip 24/24] clk: renesas: rzg2l: Fix clk status function Lad Prabhakar
2021-12-17 7:42 ` [cip-dev] [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK nobuhiro1.iwamatsu
2021-12-17 10:39 ` Pavel Machek
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