From: Anup Patel <anup@brainfault.org> To: Peter Maydell <peter.maydell@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Anup Patel <anup@brainfault.org>, Bin Meng <bmeng.cn@gmail.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Atish Patra <atishp@atishpatra.org> Subject: [PATCH v6 00/23] QEMU RISC-V AIA support Date: Thu, 30 Dec 2021 18:05:16 +0530 [thread overview] Message-ID: <20211230123539.52786-1-anup@brainfault.org> (raw) From: Anup Patel <anup.patel@wdc.com> The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here: https://github.com/riscv/riscv-aia/releases/download/0.2-draft.28/riscv-interrupts-028.pdf This series adds RISC-V AIA support in QEMU which includes emulating all AIA local CSRs, APLIC, and IMSIC. Only AIA local interrupt filtering is not implemented because we don't have any local interrupt greater than 12. To enable AIA in QEMU, use one of the following: 1) Only AIA local interrupt CSRs: Pass "x-aia=true" as CPU paramenter in the QEMU command-line 2) Only APLIC for virt machine: Pass "aia=aplic" as machine parameter in the QEMU command-line 3) Both APLIC and IMSIC for virt machine: Pass "aia=aplic-imsic" as machine parameter in the QEMU command-line 4) Both APLIC and IMSIC with 2 guest files for virt machine: Pass "aia=aplic-imsic,aia-guests=2" as machine parameter in the QEMU command-line To test series, we require OpenSBI and Linux with AIA support which can be found in riscv_aia_v1 branch at: https://github.com/avpatel/opensbi.git https://github.com/avpatel/linux.git This series can be found riscv_aia_v6 branch at: https://github.com/avpatel/qemu.git Changes since v5: - Moved VSTOPI_NUM_SRCS define to top of the file in PATCH13 - Fixed typo in PATCH16 Changes since v4: - Changed IRQ_LOCAL_MAX to 16 in PATCH2 - Fixed typo in PATCH10 - Replaced TARGET_LONG_BITS with riscv_cpu_mxl_bits(env) in PATCH11 - Replaced TARGET_LONG_BITS with riscv_cpu_mxl_bits(env) in PATCH14 - Replaced TARGET_LONG_BITS with riscv_cpu_mxl_bits(env) in PATCH15 - Replaced TARGET_LONG_BITS with xlen passed via ireg callback in PATCH20 - Retrict maximum IMSIC guest files per-HART of virt machine to 7 in PATCH21. - Added separate PATCH23 to increase maximum number of allowed CPUs for virt machine Changes since v3: - Replaced "aplic,xyz" and "imsic,xyz" DT properties with "riscv,xyz" DT properties because "aplic" and "imsic" are not valid vendor names required by Linux DT schema checker. Changes since v2: - Update PATCH4 to check and inject interrupt after V=1 when transitioning from V=0 to V=1 Changes since v1: - Revamped whole series and created more granular patches - Added HGEIE and HGEIP CSR emulation for H-extension - Added APLIC emulation - Added IMSIC emulation Anup Patel (23): target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode target/riscv: Implement SGEIP bit in hip and hie CSRs target/riscv: Implement hgeie and hgeip CSRs target/riscv: Improve delivery of guest external interrupts target/riscv: Allow setting CPU feature from machine/device emulation target/riscv: Add AIA cpu feature target/riscv: Add defines for AIA CSRs target/riscv: Allow AIA device emulation to set ireg rmw callback target/riscv: Implement AIA local interrupt priorities target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 target/riscv: Implement AIA hvictl and hviprioX CSRs target/riscv: Implement AIA interrupt filtering CSRs target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs target/riscv: Implement AIA xiselect and xireg CSRs target/riscv: Implement AIA IMSIC interface CSRs hw/riscv: virt: Use AIA INTC compatible string when available target/riscv: Allow users to force enable AIA CSRs in HART hw/intc: Add RISC-V AIA APLIC device emulation hw/riscv: virt: Add optional AIA APLIC support to virt machine hw/intc: Add RISC-V AIA IMSIC device emulation hw/riscv: virt: Add optional AIA IMSIC support to virt machine docs/system: riscv: Document AIA options for virt machine hw/riscv: virt: Increase maximum number of allowed CPUs docs/system/riscv/virt.rst | 16 + hw/intc/Kconfig | 6 + hw/intc/meson.build | 2 + hw/intc/riscv_aplic.c | 970 +++++++++++++++++++++++++ hw/intc/riscv_imsic.c | 447 ++++++++++++ hw/riscv/Kconfig | 2 + hw/riscv/virt.c | 708 +++++++++++++++--- include/hw/intc/riscv_aplic.h | 79 ++ include/hw/intc/riscv_imsic.h | 68 ++ include/hw/riscv/virt.h | 42 +- target/riscv/cpu.c | 97 ++- target/riscv/cpu.h | 72 +- target/riscv/cpu_bits.h | 131 ++++ target/riscv/cpu_helper.c | 293 +++++++- target/riscv/csr.c | 1279 ++++++++++++++++++++++++++++++--- target/riscv/machine.c | 24 +- 16 files changed, 3938 insertions(+), 298 deletions(-) create mode 100644 hw/intc/riscv_aplic.c create mode 100644 hw/intc/riscv_imsic.c create mode 100644 include/hw/intc/riscv_aplic.h create mode 100644 include/hw/intc/riscv_imsic.h -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org> To: Peter Maydell <peter.maydell@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Atish Patra <atishp@atishpatra.org>, Anup Patel <anup@brainfault.org>, Bin Meng <bmeng.cn@gmail.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v6 00/23] QEMU RISC-V AIA support Date: Thu, 30 Dec 2021 18:05:16 +0530 [thread overview] Message-ID: <20211230123539.52786-1-anup@brainfault.org> (raw) From: Anup Patel <anup.patel@wdc.com> The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here: https://github.com/riscv/riscv-aia/releases/download/0.2-draft.28/riscv-interrupts-028.pdf This series adds RISC-V AIA support in QEMU which includes emulating all AIA local CSRs, APLIC, and IMSIC. Only AIA local interrupt filtering is not implemented because we don't have any local interrupt greater than 12. To enable AIA in QEMU, use one of the following: 1) Only AIA local interrupt CSRs: Pass "x-aia=true" as CPU paramenter in the QEMU command-line 2) Only APLIC for virt machine: Pass "aia=aplic" as machine parameter in the QEMU command-line 3) Both APLIC and IMSIC for virt machine: Pass "aia=aplic-imsic" as machine parameter in the QEMU command-line 4) Both APLIC and IMSIC with 2 guest files for virt machine: Pass "aia=aplic-imsic,aia-guests=2" as machine parameter in the QEMU command-line To test series, we require OpenSBI and Linux with AIA support which can be found in riscv_aia_v1 branch at: https://github.com/avpatel/opensbi.git https://github.com/avpatel/linux.git This series can be found riscv_aia_v6 branch at: https://github.com/avpatel/qemu.git Changes since v5: - Moved VSTOPI_NUM_SRCS define to top of the file in PATCH13 - Fixed typo in PATCH16 Changes since v4: - Changed IRQ_LOCAL_MAX to 16 in PATCH2 - Fixed typo in PATCH10 - Replaced TARGET_LONG_BITS with riscv_cpu_mxl_bits(env) in PATCH11 - Replaced TARGET_LONG_BITS with riscv_cpu_mxl_bits(env) in PATCH14 - Replaced TARGET_LONG_BITS with riscv_cpu_mxl_bits(env) in PATCH15 - Replaced TARGET_LONG_BITS with xlen passed via ireg callback in PATCH20 - Retrict maximum IMSIC guest files per-HART of virt machine to 7 in PATCH21. - Added separate PATCH23 to increase maximum number of allowed CPUs for virt machine Changes since v3: - Replaced "aplic,xyz" and "imsic,xyz" DT properties with "riscv,xyz" DT properties because "aplic" and "imsic" are not valid vendor names required by Linux DT schema checker. Changes since v2: - Update PATCH4 to check and inject interrupt after V=1 when transitioning from V=0 to V=1 Changes since v1: - Revamped whole series and created more granular patches - Added HGEIE and HGEIP CSR emulation for H-extension - Added APLIC emulation - Added IMSIC emulation Anup Patel (23): target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode target/riscv: Implement SGEIP bit in hip and hie CSRs target/riscv: Implement hgeie and hgeip CSRs target/riscv: Improve delivery of guest external interrupts target/riscv: Allow setting CPU feature from machine/device emulation target/riscv: Add AIA cpu feature target/riscv: Add defines for AIA CSRs target/riscv: Allow AIA device emulation to set ireg rmw callback target/riscv: Implement AIA local interrupt priorities target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 target/riscv: Implement AIA hvictl and hviprioX CSRs target/riscv: Implement AIA interrupt filtering CSRs target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs target/riscv: Implement AIA xiselect and xireg CSRs target/riscv: Implement AIA IMSIC interface CSRs hw/riscv: virt: Use AIA INTC compatible string when available target/riscv: Allow users to force enable AIA CSRs in HART hw/intc: Add RISC-V AIA APLIC device emulation hw/riscv: virt: Add optional AIA APLIC support to virt machine hw/intc: Add RISC-V AIA IMSIC device emulation hw/riscv: virt: Add optional AIA IMSIC support to virt machine docs/system: riscv: Document AIA options for virt machine hw/riscv: virt: Increase maximum number of allowed CPUs docs/system/riscv/virt.rst | 16 + hw/intc/Kconfig | 6 + hw/intc/meson.build | 2 + hw/intc/riscv_aplic.c | 970 +++++++++++++++++++++++++ hw/intc/riscv_imsic.c | 447 ++++++++++++ hw/riscv/Kconfig | 2 + hw/riscv/virt.c | 708 +++++++++++++++--- include/hw/intc/riscv_aplic.h | 79 ++ include/hw/intc/riscv_imsic.h | 68 ++ include/hw/riscv/virt.h | 42 +- target/riscv/cpu.c | 97 ++- target/riscv/cpu.h | 72 +- target/riscv/cpu_bits.h | 131 ++++ target/riscv/cpu_helper.c | 293 +++++++- target/riscv/csr.c | 1279 ++++++++++++++++++++++++++++++--- target/riscv/machine.c | 24 +- 16 files changed, 3938 insertions(+), 298 deletions(-) create mode 100644 hw/intc/riscv_aplic.c create mode 100644 hw/intc/riscv_imsic.c create mode 100644 include/hw/intc/riscv_aplic.h create mode 100644 include/hw/intc/riscv_imsic.h -- 2.25.1
next reply other threads:[~2021-12-30 12:37 UTC|newest] Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-30 12:35 Anup Patel [this message] 2021-12-30 12:35 ` [PATCH v6 00/23] QEMU RISC-V AIA support Anup Patel 2021-12-30 12:35 ` [PATCH v6 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-12 12:29 ` Frank Chang 2022-01-12 12:29 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-13 14:35 ` Frank Chang 2022-01-13 14:35 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 03/23] target/riscv: Implement hgeie and hgeip CSRs Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-14 6:37 ` Frank Chang 2022-01-14 6:37 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 04/23] target/riscv: Improve delivery of guest external interrupts Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-13 7:51 ` Frank Chang 2022-01-13 7:51 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 05/23] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-12 12:34 ` Frank Chang 2022-01-12 12:34 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 06/23] target/riscv: Add AIA cpu feature Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-12 12:34 ` Frank Chang 2022-01-12 12:34 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 07/23] target/riscv: Add defines for AIA CSRs Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-12 12:57 ` Frank Chang 2022-01-12 12:57 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-12 12:59 ` Frank Chang 2022-01-12 12:59 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-10 13:08 ` Frank Chang 2022-01-10 13:08 ` Frank Chang 2022-01-11 17:18 ` Anup Patel 2022-01-11 17:18 ` Anup Patel 2022-01-12 3:00 ` Frank Chang 2022-01-12 3:00 ` Frank Chang 2022-01-13 10:45 ` Anup Patel 2022-01-13 10:45 ` Anup Patel 2022-01-13 14:21 ` Frank Chang 2022-01-13 14:21 ` Frank Chang 2022-01-10 13:25 ` Frank Chang 2022-01-10 13:25 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-14 9:48 ` Frank Chang 2022-01-14 9:48 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-12 13:15 ` Frank Chang 2022-01-12 13:15 ` Frank Chang 2022-01-13 10:49 ` Anup Patel 2022-01-13 10:49 ` Anup Patel 2021-12-30 12:35 ` [PATCH v6 12/23] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-11 6:00 ` Frank Chang 2022-01-11 6:00 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-12 12:15 ` Frank Chang 2022-01-12 12:15 ` Frank Chang 2022-01-13 10:48 ` Anup Patel 2022-01-13 10:48 ` Anup Patel 2021-12-30 12:35 ` [PATCH v6 14/23] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-12 16:40 ` Frank Chang 2022-01-12 16:40 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 15/23] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-05 3:30 ` Frank Chang 2022-01-05 3:30 ` Frank Chang 2022-01-08 12:03 ` Anup Patel 2022-01-08 12:03 ` Anup Patel 2021-12-30 12:35 ` [PATCH v6 16/23] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-12 16:47 ` Frank Chang 2022-01-12 16:47 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 17/23] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-12 13:19 ` Frank Chang 2022-01-12 13:19 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-07 8:52 ` Frank Chang 2022-01-07 8:52 ` Frank Chang 2022-01-08 13:28 ` Anup Patel 2022-01-08 13:28 ` Anup Patel 2022-01-08 6:35 ` Frank Chang 2022-01-08 6:35 ` Frank Chang 2022-01-08 12:00 ` Anup Patel 2022-01-08 12:00 ` Anup Patel 2022-01-14 12:02 ` Frank Chang 2022-01-14 12:02 ` Frank Chang 2022-01-14 12:59 ` Anup Patel 2022-01-14 12:59 ` Anup Patel 2021-12-30 12:35 ` [PATCH v6 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel 2021-12-30 12:35 ` Anup Patel 2021-12-30 12:35 ` [PATCH v6 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-13 7:26 ` Frank Chang 2022-01-13 7:26 ` Frank Chang 2022-01-13 12:22 ` Anup Patel 2022-01-13 12:22 ` Anup Patel 2021-12-30 12:35 ` [PATCH v6 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel 2021-12-30 12:35 ` Anup Patel 2021-12-30 12:35 ` [PATCH v6 22/23] docs/system: riscv: Document AIA options for " Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-12 13:23 ` Frank Chang 2022-01-12 13:23 ` Frank Chang 2021-12-30 12:35 ` [PATCH v6 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs Anup Patel 2021-12-30 12:35 ` Anup Patel 2022-01-05 21:50 ` Alistair Francis 2022-01-05 21:50 ` Alistair Francis 2022-01-12 13:26 ` Frank Chang 2022-01-12 13:26 ` Frank Chang
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