From: Neil Armstrong <narmstrong@baylibre.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Neil Armstrong <narmstrong@baylibre.com>
Subject: [PATCH 4/6] drm/meson: vclk: add DSI clock config
Date: Fri, 7 Jan 2022 15:55:13 +0100 [thread overview]
Message-ID: <20220107145515.613009-5-narmstrong@baylibre.com> (raw)
In-Reply-To: <20220107145515.613009-1-narmstrong@baylibre.com>
The DSI path used the ENCL pixel encoder, thus this adds a clock
config using the HDMI PLL in order to feed the ENCL encoder via the
VCLK2 path and the CTS_ENCL clock output.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_vclk.c | 47 ++++++++++++++++++++++++++++++
drivers/gpu/drm/meson/meson_vclk.h | 1 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
index 2a82119eb58e..5e4d982be1c8 100644
--- a/drivers/gpu/drm/meson/meson_vclk.c
+++ b/drivers/gpu/drm/meson/meson_vclk.c
@@ -55,6 +55,8 @@
#define VCLK2_DIV_MASK 0xff
#define VCLK2_DIV_EN BIT(16)
#define VCLK2_DIV_RESET BIT(17)
+#define CTS_ENCL_SEL_MASK (0xf << 12)
+#define CTS_ENCL_SEL_SHIFT 12
#define CTS_VDAC_SEL_MASK (0xf << 28)
#define CTS_VDAC_SEL_SHIFT 28
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
@@ -83,6 +85,7 @@
#define VCLK_DIV12_EN BIT(4)
#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
#define CTS_ENCI_EN BIT(0)
+#define CTS_ENCL_EN BIT(3)
#define CTS_ENCP_EN BIT(2)
#define CTS_VDAC_EN BIT(4)
#define HDMI_TX_PIXEL_EN BIT(5)
@@ -1024,6 +1027,47 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
}
+static void meson_dsi_clock_config(struct meson_drm *priv, unsigned int freq)
+{
+ meson_hdmi_pll_generic_set(priv, freq * 10);
+
+ /* Setup vid_pll divider value /5 */
+ meson_vid_pll_set(priv, VID_PLL_DIV_5);
+
+ /* Disable VCLK2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
+
+ /* Setup the VCLK2 divider value /2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_MASK, 2 - 1);
+
+ /* select vid_pll for vclk2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
+ VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
+
+ /* enable vclk2 gate */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
+
+ /* select vclk2_div1 for encl */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
+ CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
+
+ /* release vclk2_div_reset and enable vclk2_div */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_EN | VCLK2_DIV_RESET,
+ VCLK2_DIV_EN);
+
+ /* enable vclk2_div1 gate */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_DIV1_EN, VCLK2_DIV1_EN);
+
+ /* reset vclk2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, 0);
+
+ /* enable encl_clk */
+ regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, CTS_ENCL_EN, CTS_ENCL_EN);
+
+ usleep_range(10000, 11000);
+}
+
void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
unsigned int phy_freq, unsigned int vclk_freq,
unsigned int venc_freq, unsigned int dac_freq,
@@ -1050,6 +1094,9 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
meson_vclk_set(priv, phy_freq, 0, 0, 0,
VID_PLL_DIV_5, 2, 1, 1, false, false);
return;
+ } else if (target == MESON_VCLK_TARGET_DSI) {
+ meson_dsi_clock_config(priv, phy_freq);
+ return;
}
hdmi_tx_div = vclk_freq / dac_freq;
diff --git a/drivers/gpu/drm/meson/meson_vclk.h b/drivers/gpu/drm/meson/meson_vclk.h
index 60617aaf18dd..1152b3af8d2e 100644
--- a/drivers/gpu/drm/meson/meson_vclk.h
+++ b/drivers/gpu/drm/meson/meson_vclk.h
@@ -17,6 +17,7 @@ enum {
MESON_VCLK_TARGET_CVBS = 0,
MESON_VCLK_TARGET_HDMI = 1,
MESON_VCLK_TARGET_DMT = 2,
+ MESON_VCLK_TARGET_DSI = 3,
};
/* 27MHz is the CVBS Pixel Clock */
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Neil Armstrong <narmstrong@baylibre.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Neil Armstrong <narmstrong@baylibre.com>
Subject: [PATCH 4/6] drm/meson: vclk: add DSI clock config
Date: Fri, 7 Jan 2022 15:55:13 +0100 [thread overview]
Message-ID: <20220107145515.613009-5-narmstrong@baylibre.com> (raw)
In-Reply-To: <20220107145515.613009-1-narmstrong@baylibre.com>
The DSI path used the ENCL pixel encoder, thus this adds a clock
config using the HDMI PLL in order to feed the ENCL encoder via the
VCLK2 path and the CTS_ENCL clock output.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_vclk.c | 47 ++++++++++++++++++++++++++++++
drivers/gpu/drm/meson/meson_vclk.h | 1 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
index 2a82119eb58e..5e4d982be1c8 100644
--- a/drivers/gpu/drm/meson/meson_vclk.c
+++ b/drivers/gpu/drm/meson/meson_vclk.c
@@ -55,6 +55,8 @@
#define VCLK2_DIV_MASK 0xff
#define VCLK2_DIV_EN BIT(16)
#define VCLK2_DIV_RESET BIT(17)
+#define CTS_ENCL_SEL_MASK (0xf << 12)
+#define CTS_ENCL_SEL_SHIFT 12
#define CTS_VDAC_SEL_MASK (0xf << 28)
#define CTS_VDAC_SEL_SHIFT 28
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
@@ -83,6 +85,7 @@
#define VCLK_DIV12_EN BIT(4)
#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
#define CTS_ENCI_EN BIT(0)
+#define CTS_ENCL_EN BIT(3)
#define CTS_ENCP_EN BIT(2)
#define CTS_VDAC_EN BIT(4)
#define HDMI_TX_PIXEL_EN BIT(5)
@@ -1024,6 +1027,47 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
}
+static void meson_dsi_clock_config(struct meson_drm *priv, unsigned int freq)
+{
+ meson_hdmi_pll_generic_set(priv, freq * 10);
+
+ /* Setup vid_pll divider value /5 */
+ meson_vid_pll_set(priv, VID_PLL_DIV_5);
+
+ /* Disable VCLK2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
+
+ /* Setup the VCLK2 divider value /2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_MASK, 2 - 1);
+
+ /* select vid_pll for vclk2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
+ VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
+
+ /* enable vclk2 gate */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
+
+ /* select vclk2_div1 for encl */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
+ CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
+
+ /* release vclk2_div_reset and enable vclk2_div */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_EN | VCLK2_DIV_RESET,
+ VCLK2_DIV_EN);
+
+ /* enable vclk2_div1 gate */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_DIV1_EN, VCLK2_DIV1_EN);
+
+ /* reset vclk2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, 0);
+
+ /* enable encl_clk */
+ regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, CTS_ENCL_EN, CTS_ENCL_EN);
+
+ usleep_range(10000, 11000);
+}
+
void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
unsigned int phy_freq, unsigned int vclk_freq,
unsigned int venc_freq, unsigned int dac_freq,
@@ -1050,6 +1094,9 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
meson_vclk_set(priv, phy_freq, 0, 0, 0,
VID_PLL_DIV_5, 2, 1, 1, false, false);
return;
+ } else if (target == MESON_VCLK_TARGET_DSI) {
+ meson_dsi_clock_config(priv, phy_freq);
+ return;
}
hdmi_tx_div = vclk_freq / dac_freq;
diff --git a/drivers/gpu/drm/meson/meson_vclk.h b/drivers/gpu/drm/meson/meson_vclk.h
index 60617aaf18dd..1152b3af8d2e 100644
--- a/drivers/gpu/drm/meson/meson_vclk.h
+++ b/drivers/gpu/drm/meson/meson_vclk.h
@@ -17,6 +17,7 @@ enum {
MESON_VCLK_TARGET_CVBS = 0,
MESON_VCLK_TARGET_HDMI = 1,
MESON_VCLK_TARGET_DMT = 2,
+ MESON_VCLK_TARGET_DSI = 3,
};
/* 27MHz is the CVBS Pixel Clock */
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Neil Armstrong <narmstrong@baylibre.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Neil Armstrong <narmstrong@baylibre.com>
Subject: [PATCH 4/6] drm/meson: vclk: add DSI clock config
Date: Fri, 7 Jan 2022 15:55:13 +0100 [thread overview]
Message-ID: <20220107145515.613009-5-narmstrong@baylibre.com> (raw)
In-Reply-To: <20220107145515.613009-1-narmstrong@baylibre.com>
The DSI path used the ENCL pixel encoder, thus this adds a clock
config using the HDMI PLL in order to feed the ENCL encoder via the
VCLK2 path and the CTS_ENCL clock output.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_vclk.c | 47 ++++++++++++++++++++++++++++++
drivers/gpu/drm/meson/meson_vclk.h | 1 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
index 2a82119eb58e..5e4d982be1c8 100644
--- a/drivers/gpu/drm/meson/meson_vclk.c
+++ b/drivers/gpu/drm/meson/meson_vclk.c
@@ -55,6 +55,8 @@
#define VCLK2_DIV_MASK 0xff
#define VCLK2_DIV_EN BIT(16)
#define VCLK2_DIV_RESET BIT(17)
+#define CTS_ENCL_SEL_MASK (0xf << 12)
+#define CTS_ENCL_SEL_SHIFT 12
#define CTS_VDAC_SEL_MASK (0xf << 28)
#define CTS_VDAC_SEL_SHIFT 28
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
@@ -83,6 +85,7 @@
#define VCLK_DIV12_EN BIT(4)
#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
#define CTS_ENCI_EN BIT(0)
+#define CTS_ENCL_EN BIT(3)
#define CTS_ENCP_EN BIT(2)
#define CTS_VDAC_EN BIT(4)
#define HDMI_TX_PIXEL_EN BIT(5)
@@ -1024,6 +1027,47 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
}
+static void meson_dsi_clock_config(struct meson_drm *priv, unsigned int freq)
+{
+ meson_hdmi_pll_generic_set(priv, freq * 10);
+
+ /* Setup vid_pll divider value /5 */
+ meson_vid_pll_set(priv, VID_PLL_DIV_5);
+
+ /* Disable VCLK2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
+
+ /* Setup the VCLK2 divider value /2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_MASK, 2 - 1);
+
+ /* select vid_pll for vclk2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
+ VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
+
+ /* enable vclk2 gate */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
+
+ /* select vclk2_div1 for encl */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
+ CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
+
+ /* release vclk2_div_reset and enable vclk2_div */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_EN | VCLK2_DIV_RESET,
+ VCLK2_DIV_EN);
+
+ /* enable vclk2_div1 gate */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_DIV1_EN, VCLK2_DIV1_EN);
+
+ /* reset vclk2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, 0);
+
+ /* enable encl_clk */
+ regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, CTS_ENCL_EN, CTS_ENCL_EN);
+
+ usleep_range(10000, 11000);
+}
+
void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
unsigned int phy_freq, unsigned int vclk_freq,
unsigned int venc_freq, unsigned int dac_freq,
@@ -1050,6 +1094,9 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
meson_vclk_set(priv, phy_freq, 0, 0, 0,
VID_PLL_DIV_5, 2, 1, 1, false, false);
return;
+ } else if (target == MESON_VCLK_TARGET_DSI) {
+ meson_dsi_clock_config(priv, phy_freq);
+ return;
}
hdmi_tx_div = vclk_freq / dac_freq;
diff --git a/drivers/gpu/drm/meson/meson_vclk.h b/drivers/gpu/drm/meson/meson_vclk.h
index 60617aaf18dd..1152b3af8d2e 100644
--- a/drivers/gpu/drm/meson/meson_vclk.h
+++ b/drivers/gpu/drm/meson/meson_vclk.h
@@ -17,6 +17,7 @@ enum {
MESON_VCLK_TARGET_CVBS = 0,
MESON_VCLK_TARGET_HDMI = 1,
MESON_VCLK_TARGET_DMT = 2,
+ MESON_VCLK_TARGET_DSI = 3,
};
/* 27MHz is the CVBS Pixel Clock */
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Neil Armstrong <narmstrong@baylibre.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Neil Armstrong <narmstrong@baylibre.com>
Subject: [PATCH 4/6] drm/meson: vclk: add DSI clock config
Date: Fri, 7 Jan 2022 15:55:13 +0100 [thread overview]
Message-ID: <20220107145515.613009-5-narmstrong@baylibre.com> (raw)
In-Reply-To: <20220107145515.613009-1-narmstrong@baylibre.com>
The DSI path used the ENCL pixel encoder, thus this adds a clock
config using the HDMI PLL in order to feed the ENCL encoder via the
VCLK2 path and the CTS_ENCL clock output.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_vclk.c | 47 ++++++++++++++++++++++++++++++
drivers/gpu/drm/meson/meson_vclk.h | 1 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
index 2a82119eb58e..5e4d982be1c8 100644
--- a/drivers/gpu/drm/meson/meson_vclk.c
+++ b/drivers/gpu/drm/meson/meson_vclk.c
@@ -55,6 +55,8 @@
#define VCLK2_DIV_MASK 0xff
#define VCLK2_DIV_EN BIT(16)
#define VCLK2_DIV_RESET BIT(17)
+#define CTS_ENCL_SEL_MASK (0xf << 12)
+#define CTS_ENCL_SEL_SHIFT 12
#define CTS_VDAC_SEL_MASK (0xf << 28)
#define CTS_VDAC_SEL_SHIFT 28
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
@@ -83,6 +85,7 @@
#define VCLK_DIV12_EN BIT(4)
#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
#define CTS_ENCI_EN BIT(0)
+#define CTS_ENCL_EN BIT(3)
#define CTS_ENCP_EN BIT(2)
#define CTS_VDAC_EN BIT(4)
#define HDMI_TX_PIXEL_EN BIT(5)
@@ -1024,6 +1027,47 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
}
+static void meson_dsi_clock_config(struct meson_drm *priv, unsigned int freq)
+{
+ meson_hdmi_pll_generic_set(priv, freq * 10);
+
+ /* Setup vid_pll divider value /5 */
+ meson_vid_pll_set(priv, VID_PLL_DIV_5);
+
+ /* Disable VCLK2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
+
+ /* Setup the VCLK2 divider value /2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_MASK, 2 - 1);
+
+ /* select vid_pll for vclk2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
+ VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
+
+ /* enable vclk2 gate */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
+
+ /* select vclk2_div1 for encl */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
+ CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
+
+ /* release vclk2_div_reset and enable vclk2_div */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_EN | VCLK2_DIV_RESET,
+ VCLK2_DIV_EN);
+
+ /* enable vclk2_div1 gate */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_DIV1_EN, VCLK2_DIV1_EN);
+
+ /* reset vclk2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, 0);
+
+ /* enable encl_clk */
+ regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, CTS_ENCL_EN, CTS_ENCL_EN);
+
+ usleep_range(10000, 11000);
+}
+
void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
unsigned int phy_freq, unsigned int vclk_freq,
unsigned int venc_freq, unsigned int dac_freq,
@@ -1050,6 +1094,9 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
meson_vclk_set(priv, phy_freq, 0, 0, 0,
VID_PLL_DIV_5, 2, 1, 1, false, false);
return;
+ } else if (target == MESON_VCLK_TARGET_DSI) {
+ meson_dsi_clock_config(priv, phy_freq);
+ return;
}
hdmi_tx_div = vclk_freq / dac_freq;
diff --git a/drivers/gpu/drm/meson/meson_vclk.h b/drivers/gpu/drm/meson/meson_vclk.h
index 60617aaf18dd..1152b3af8d2e 100644
--- a/drivers/gpu/drm/meson/meson_vclk.h
+++ b/drivers/gpu/drm/meson/meson_vclk.h
@@ -17,6 +17,7 @@ enum {
MESON_VCLK_TARGET_CVBS = 0,
MESON_VCLK_TARGET_HDMI = 1,
MESON_VCLK_TARGET_DMT = 2,
+ MESON_VCLK_TARGET_DSI = 3,
};
/* 27MHz is the CVBS Pixel Clock */
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-01-07 14:55 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-07 14:55 [PATCH 0/6] drm/meson: add support for MIPI DSI Display Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` [PATCH 1/6] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-12 1:54 ` Rob Herring
2022-01-12 1:54 ` Rob Herring
2022-01-12 1:54 ` Rob Herring
2022-01-12 1:54 ` Rob Herring
2022-01-07 14:55 ` [PATCH 2/6] dt-bindings: display: meson-vpu: add third DPI output port Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 22:14 ` Martin Blumenstingl
2022-01-07 22:14 ` Martin Blumenstingl
2022-01-07 22:14 ` Martin Blumenstingl
2022-01-07 22:14 ` Martin Blumenstingl
2022-01-12 1:54 ` Rob Herring
2022-01-12 1:54 ` Rob Herring
2022-01-12 1:54 ` Rob Herring
2022-01-12 1:54 ` Rob Herring
2022-01-07 14:55 ` [PATCH 3/6] drm/meson: venc: add ENCL encoder setup for MIPI-DSI output Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 22:33 ` Martin Blumenstingl
2022-01-07 22:33 ` Martin Blumenstingl
2022-01-07 22:33 ` Martin Blumenstingl
2022-01-07 22:33 ` Martin Blumenstingl
2022-01-10 9:45 ` Neil Armstrong
2022-01-10 9:45 ` Neil Armstrong
2022-01-10 9:45 ` Neil Armstrong
2022-01-10 9:45 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong [this message]
2022-01-07 14:55 ` [PATCH 4/6] drm/meson: vclk: add DSI clock config Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` [PATCH 5/6] drm/meson: add DSI encoder Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 22:35 ` Martin Blumenstingl
2022-01-07 22:35 ` Martin Blumenstingl
2022-01-07 22:35 ` Martin Blumenstingl
2022-01-07 22:35 ` Martin Blumenstingl
2022-01-10 9:46 ` Neil Armstrong
2022-01-10 9:46 ` Neil Armstrong
2022-01-10 9:46 ` Neil Armstrong
2022-01-10 9:46 ` Neil Armstrong
2022-01-08 18:54 ` kernel test robot
2022-01-08 18:54 ` kernel test robot
2022-01-07 14:55 ` [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 22:49 ` Martin Blumenstingl
2022-01-07 22:49 ` Martin Blumenstingl
2022-01-07 22:49 ` Martin Blumenstingl
2022-01-07 22:49 ` Martin Blumenstingl
2022-01-10 9:51 ` Neil Armstrong
2022-01-10 9:51 ` Neil Armstrong
2022-01-10 9:51 ` Neil Armstrong
2022-01-10 9:51 ` Neil Armstrong
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