From: Biju Das <biju.das.jz@bp.renesas.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 3/4] arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board
Date: Wed, 19 Jan 2022 09:52:44 +0000 [thread overview]
Message-ID: <20220119095245.5611-3-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220119095245.5611-1-biju.das.jz@bp.renesas.com>
SCIF1 interface is available on PMOD1 connector (CN7) on carrier board.
This patch adds pinmux and scif1 node to carrier board dtsi file for
RZ/G2LC SMARC EVK.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 +++++
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 26 +++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index 1032f6563515..ec9e08ec0822 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -17,6 +17,13 @@
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
+ scif1_pins: scif1 {
+ pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
+ <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
+ <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
+ };
+
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index a998b4dbf35c..9add19eb5511 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -34,3 +34,29 @@
#include "rzg2lc-smarc-som.dtsi"
#include "rzg2lc-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"
+
+/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0 1
+
+/ {
+ aliases {
+ serial1 = &scif1;
+ };
+};
+
+/*
+ * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
+ * SW1 should be at position 2->3 so that SER0_CTS# line is activated
+ * SW2 should be at position 2->3 so that SER0_TX line is activated
+ * SW3 should be at position 2->3 so that SER0_RX line is activated
+ * SW4 should be at position 2->3 so that SER0_RTS# line is activated
+ */
+#if (!SW_SCIF_CAN && PMOD1_SER0)
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ status = "okay";
+};
+#endif
--
2.17.1
next prev parent reply other threads:[~2022-01-19 9:52 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-19 9:52 [PATCH 1/4] arm64: dts: renesas: rzg2l-smarc: Add common dtsi file Biju Das
2022-01-19 9:52 ` [PATCH 2/4] arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings Biju Das
2022-01-19 9:52 ` Biju Das [this message]
2022-01-19 9:52 ` [PATCH 4/4] arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1 Biju Das
2022-02-01 16:46 ` [PATCH 1/4] arm64: dts: renesas: rzg2l-smarc: Add common dtsi file Geert Uytterhoeven
2022-02-01 17:09 ` Biju Das
2022-02-01 18:07 ` Geert Uytterhoeven
2022-02-01 18:09 ` Biju Das
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