From: Ansuel Smith <ansuelsmth@gmail.com>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Taniya Das <tdas@codeaurora.org>,
Ansuel Smith <ansuelsmth@gmail.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 12/15] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks
Date: Fri, 21 Jan 2022 00:20:25 +0100 [thread overview]
Message-ID: <20220120232028.6738-13-ansuelsmth@gmail.com> (raw)
In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com>
Add missing CryptoEngine clocks and pll11 required clock.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++
1 file changed, 244 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index dbd61e4844b0..a86d1504a149 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -256,6 +256,24 @@ static struct clk_pll pll18 = {
},
};
+static struct clk_pll pll11 = {
+ .l_reg = 0x3184,
+ .m_reg = 0x3188,
+ .n_reg = 0x318c,
+ .config_reg = 0x3194,
+ .mode_reg = 0x3180,
+ .status_reg = 0x3198,
+ .status_bit = 16,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pll11",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "pxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
enum {
P_PXO,
P_PLL8,
@@ -264,6 +282,7 @@ enum {
P_CXO,
P_PLL14,
P_PLL18,
+ P_PLL11,
};
static const struct parent_map gcc_pxo_pll8_map[] = {
@@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
{ .hw = &pll18.clkr.hw },
};
+static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 4 },
+ { P_PLL0, 2 },
+ { P_PLL14, 5 },
+ { P_PLL18, 1 },
+ { P_PLL11, 3 },
+};
+
+static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
+ { .fw_name = "pxo" },
+ { .hw = &pll8_vote.hw },
+ { .hw = &pll0_vote.hw },
+ { .hw = &pll14.clkr.hw },
+ { .hw = &pll18.clkr.hw },
+ { .hw = &pll11.clkr.hw },
+
+};
+
+static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
+ { P_PXO, 0 },
+ { P_PLL3, 6 },
+ { P_PLL0, 2 },
+ { P_PLL14, 5 },
+ { P_PLL18, 1 },
+ { P_PLL11, 3 },
+};
+
+static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
+ { .fw_name = "pxo" },
+ { .hw = &pll3.clkr.hw },
+ { .hw = &pll0_vote.hw },
+ { .hw = &pll14.clkr.hw },
+ { .hw = &pll18.clkr.hw },
+ { .hw = &pll11.clkr.hw },
+
+};
+
static struct freq_tbl clk_tbl_gsbi_uart[] = {
{ 1843200, P_PLL8, 2, 6, 625 },
{ 3686400, P_PLL8, 2, 12, 625 },
@@ -2818,6 +2875,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
},
};
+static const struct freq_tbl clk_tbl_ce5_core[] = {
+ { 150000000, P_PLL3, 8, 1, 1 },
+ { 213200000, P_PLL11, 5, 1, 1 },
+ { }
+};
+
+static struct clk_dyn_rcg ce5_core_src = {
+ .ns_reg[0] = 0x36C4,
+ .ns_reg[1] = 0x36C8,
+ .bank_reg = 0x36C0,
+ .s[0] = {
+ .src_sel_shift = 0,
+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
+ },
+ .s[1] = {
+ .src_sel_shift = 0,
+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
+ },
+ .p[0] = {
+ .pre_div_shift = 3,
+ .pre_div_width = 4,
+ },
+ .p[1] = {
+ .pre_div_shift = 3,
+ .pre_div_width = 4,
+ },
+ .mux_sel_bit = 0,
+ .freq_tbl = clk_tbl_ce5_core,
+ .clkr = {
+ .enable_reg = 0x36C0,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "ce5_core_src",
+ .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11),
+ .ops = &clk_dyn_rcg_ops,
+ },
+ },
+};
+
+static struct clk_branch ce5_core_clk = {
+ .halt_reg = 0x2FDC,
+ .halt_bit = 5,
+ .hwcg_reg = 0x36CC,
+ .hwcg_bit = 6,
+ .clkr = {
+ .enable_reg = 0x36CC,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "ce5_core_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &ce5_core_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
+ { 160000000, P_PLL0, 5, 1, 1 },
+ { 213200000, P_PLL11, 5, 1, 1 },
+ { }
+};
+
+static struct clk_dyn_rcg ce5_a_clk_src = {
+ .ns_reg[0] = 0x3d84,
+ .ns_reg[1] = 0x3d88,
+ .bank_reg = 0x3d80,
+ .s[0] = {
+ .src_sel_shift = 0,
+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
+ },
+ .s[1] = {
+ .src_sel_shift = 0,
+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
+ },
+ .p[0] = {
+ .pre_div_shift = 3,
+ .pre_div_width = 4,
+ },
+ .p[1] = {
+ .pre_div_shift = 3,
+ .pre_div_width = 4,
+ },
+ .mux_sel_bit = 0,
+ .freq_tbl = clk_tbl_ce5_a_clk,
+ .clkr = {
+ .enable_reg = 0x3d80,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "ce5_a_clk_src",
+ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
+ .ops = &clk_dyn_rcg_ops,
+ },
+ },
+};
+
+static struct clk_branch ce5_a_clk = {
+ .halt_reg = 0x3c20,
+ .halt_bit = 12,
+ .hwcg_reg = 0x3d8c,
+ .hwcg_bit = 6,
+ .clkr = {
+ .enable_reg = 0x3d8c,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "ce5_a_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &ce5_a_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
+ { 160000000, P_PLL0, 5, 1, 1 },
+ { 213200000, P_PLL11, 5, 1, 1 },
+ { }
+};
+
+static struct clk_dyn_rcg ce5_h_clk_src = {
+ .ns_reg[0] = 0x3c64,
+ .ns_reg[1] = 0x3c68,
+ .bank_reg = 0x3c60,
+ .s[0] = {
+ .src_sel_shift = 0,
+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
+ },
+ .s[1] = {
+ .src_sel_shift = 0,
+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
+ },
+ .p[0] = {
+ .pre_div_shift = 3,
+ .pre_div_width = 4,
+ },
+ .p[1] = {
+ .pre_div_shift = 3,
+ .pre_div_width = 4,
+ },
+ .mux_sel_bit = 0,
+ .freq_tbl = clk_tbl_ce5_h_clk,
+ .clkr = {
+ .enable_reg = 0x3c60,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "ce5_h_clk_src",
+ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
+ .ops = &clk_dyn_rcg_ops,
+ },
+ },
+};
+
+static struct clk_branch ce5_h_clk = {
+ .halt_reg = 0x3c20,
+ .halt_bit = 11,
+ .hwcg_reg = 0x3c6c,
+ .hwcg_bit = 6,
+ .clkr = {
+ .enable_reg = 0x3c6c,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "ce5_h_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &ce5_h_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL0] = &pll0.clkr,
[PLL0_VOTE] = &pll0_vote,
@@ -2825,6 +3062,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL4_VOTE] = &pll4_vote,
[PLL8] = &pll8.clkr,
[PLL8_VOTE] = &pll8_vote,
+ [PLL11] = &pll11.clkr,
[PLL14] = &pll14.clkr,
[PLL14_VOTE] = &pll14_vote,
[PLL18] = &pll18.clkr,
@@ -2939,6 +3177,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL9] = &hfpll0.clkr,
[PLL10] = &hfpll1.clkr,
[PLL12] = &hfpll_l2.clkr,
+ [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
+ [CE5_A_CLK] = &ce5_a_clk.clkr,
+ [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
+ [CE5_H_CLK] = &ce5_h_clk.clkr,
+ [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
+ [CE5_CORE_CLK] = &ce5_core_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
--
2.33.1
next prev parent reply other threads:[~2022-01-20 23:21 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-20 23:20 [PATCH v2 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 01/15] dt-bindings: clock: permit additionalProprieties to qcom,gcc Ansuel Smith
2022-01-21 1:53 ` Rob Herring
2022-01-20 23:20 ` [PATCH v2 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation Ansuel Smith
2022-01-21 1:37 ` Rob Herring
2022-01-21 1:41 ` Ansuel Smith
2022-01-21 2:01 ` Rob Herring
2022-01-20 23:20 ` [PATCH v2 03/15] dt-bindings: clock: Document qcom,gcc-ipq8064 binding Ansuel Smith
2022-01-21 1:37 ` Rob Herring
2022-01-21 2:04 ` Rob Herring
2022-01-21 19:07 ` Ansuel Smith
2022-01-21 19:22 ` Rob Herring
2022-01-20 23:20 ` [PATCH v2 04/15] drivers: clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 05/15] drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 06/15] drivers: clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 07/15] drivers: clk: qcom: gcc-ipq806x: drop hardcoded pxo and cxo source clk Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 08/15] drivers: clk: qcom: gcc-ipq806x: add additional freq nss cores Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 09/15] drivers: clk: qcom: gcc-ipq806x: add unusued flag for critical clock Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 10/15] drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 11/15] dt-bindings: clock: add ipq8064 ce5 clk define Ansuel Smith
2022-01-20 23:20 ` Ansuel Smith [this message]
2022-01-20 23:20 ` [PATCH v2 13/15] dt-bindings: reset: add ipq8064 ce5 resets Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 14/15] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine resets Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 15/15] ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064 Ansuel Smith
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220120232028.6738-13-ansuelsmth@gmail.com \
--to=ansuelsmth@gmail.com \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=tdas@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.