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From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	Will Deacon <will@kernel.org>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
	srv_heupstream@mediatek.com,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	chengci.xu@mediatek.com, xueqi.zhang@mediatek.com,
	linux-kernel@vger.kernel.org, libo.kang@mediatek.com,
	yen-chang.chen@mediatek.com, iommu@lists.linux-foundation.org,
	yf.wang@mediatek.com, linux-mediatek@lists.infradead.org,
	Hsin-Yi Wang <hsinyi@chromium.org>,
	anan.sun@mediatek.com, Robin Murphy <robin.murphy@arm.com>,
	mingyuan.ma@mediatek.com, linux-arm-kernel@lists.infradead.org,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>
Subject: [PATCH v4 02/35] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU
Date: Tue, 25 Jan 2022 16:56:01 +0800	[thread overview]
Message-ID: <20220125085634.17972-3-yong.wu@mediatek.com> (raw)
In-Reply-To: <20220125085634.17972-1-yong.wu@mediatek.com>

In mt8195, we have a new IOMMU that is for INFRA IOMMU. its masters
mainly are PCIe and USB. Different with MM IOMMU, all these masters
connect with IOMMU directly, there is no mediatek,larbs property for
infra IOMMU.

Another thing is about PCIe ports. currently the function
"of_iommu_configure_dev_id" only support the id number is 1, But our
PCIe have two ports, one is for reading and the other is for writing.
see more about the PCIe patch in this patchset. Thus, I only list
the reading id here and add the other id in our driver.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/iommu/mediatek,iommu.yaml         | 13 ++++++++++++-
 .../dt-bindings/memory/mt8195-memory-port.h    | 18 ++++++++++++++++++
 include/dt-bindings/memory/mtk-memory-port.h   |  2 ++
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index 9b04630158c8..c528a299afa9 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -79,6 +79,7 @@ properties:
           - mediatek,mt8192-m4u  # generation two
           - mediatek,mt8195-iommu-vdo        # generation two
           - mediatek,mt8195-iommu-vpp        # generation two
+          - mediatek,mt8195-iommu-infra      # generation two
 
       - description: mt7623 generation one
         items:
@@ -129,7 +130,6 @@ required:
   - compatible
   - reg
   - interrupts
-  - mediatek,larbs
   - '#iommu-cells'
 
 allOf:
@@ -161,6 +161,17 @@ allOf:
       required:
         - power-domains
 
+  - if: # The IOMMUs don't have larbs.
+      not:
+        properties:
+          compatible:
+            contains:
+              const: mediatek,mt8195-iommu-infra
+
+    then:
+      required:
+        - mediatek,larbs
+
 additionalProperties: false
 
 examples:
diff --git a/include/dt-bindings/memory/mt8195-memory-port.h b/include/dt-bindings/memory/mt8195-memory-port.h
index eeafad451a1d..fe948fec0688 100644
--- a/include/dt-bindings/memory/mt8195-memory-port.h
+++ b/include/dt-bindings/memory/mt8195-memory-port.h
@@ -387,4 +387,22 @@
 #define M4U_PORT_L28_CAM_DRZS4NO_R1		MTK_M4U_ID(28, 5)
 #define M4U_PORT_L28_CAM_TNCSO_R1		MTK_M4U_ID(28, 6)
 
+/* Infra iommu ports */
+/* PCIe1: read: BIT16; write BIT17. */
+#define IOMMU_PORT_INFRA_PCIE1			MTK_IFAIOMMU_PERI_ID(16)
+/* PCIe0: read: BIT18; write BIT19. */
+#define IOMMU_PORT_INFRA_PCIE0			MTK_IFAIOMMU_PERI_ID(18)
+#define IOMMU_PORT_INFRA_SSUSB_P3_R		MTK_IFAIOMMU_PERI_ID(20)
+#define IOMMU_PORT_INFRA_SSUSB_P3_W		MTK_IFAIOMMU_PERI_ID(21)
+#define IOMMU_PORT_INFRA_SSUSB_P2_R		MTK_IFAIOMMU_PERI_ID(22)
+#define IOMMU_PORT_INFRA_SSUSB_P2_W		MTK_IFAIOMMU_PERI_ID(23)
+#define IOMMU_PORT_INFRA_SSUSB_P1_1_R		MTK_IFAIOMMU_PERI_ID(24)
+#define IOMMU_PORT_INFRA_SSUSB_P1_1_W		MTK_IFAIOMMU_PERI_ID(25)
+#define IOMMU_PORT_INFRA_SSUSB_P1_0_R		MTK_IFAIOMMU_PERI_ID(26)
+#define IOMMU_PORT_INFRA_SSUSB_P1_0_W		MTK_IFAIOMMU_PERI_ID(27)
+#define IOMMU_PORT_INFRA_SSUSB2_R		MTK_IFAIOMMU_PERI_ID(28)
+#define IOMMU_PORT_INFRA_SSUSB2_W		MTK_IFAIOMMU_PERI_ID(29)
+#define IOMMU_PORT_INFRA_SSUSB_R		MTK_IFAIOMMU_PERI_ID(30)
+#define IOMMU_PORT_INFRA_SSUSB_W		MTK_IFAIOMMU_PERI_ID(31)
+
 #endif
diff --git a/include/dt-bindings/memory/mtk-memory-port.h b/include/dt-bindings/memory/mtk-memory-port.h
index 7d64103209af..2f68a0511a25 100644
--- a/include/dt-bindings/memory/mtk-memory-port.h
+++ b/include/dt-bindings/memory/mtk-memory-port.h
@@ -12,4 +12,6 @@
 #define MTK_M4U_TO_LARB(id)		(((id) >> 5) & 0x1f)
 #define MTK_M4U_TO_PORT(id)		((id) & 0x1f)
 
+#define MTK_IFAIOMMU_PERI_ID(port)	MTK_M4U_ID(0, port)
+
 #endif
-- 
2.18.0

_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	Will Deacon <will@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Tomasz Figa <tfiga@chromium.org>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<iommu@lists.linux-foundation.org>,
	Hsin-Yi Wang <hsinyi@chromium.org>, <yong.wu@mediatek.com>,
	<youlin.pei@mediatek.com>, <anan.sun@mediatek.com>,
	<xueqi.zhang@mediatek.com>, <yen-chang.chen@mediatek.com>,
	"AngeloGioacchino Del Regno" 
	<angelogioacchino.delregno@collabora.com>,
	<mingyuan.ma@mediatek.com>, <yf.wang@mediatek.com>,
	<libo.kang@mediatek.com>, <chengci.xu@mediatek.com>
Subject: [PATCH v4 02/35] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU
Date: Tue, 25 Jan 2022 16:56:01 +0800	[thread overview]
Message-ID: <20220125085634.17972-3-yong.wu@mediatek.com> (raw)
In-Reply-To: <20220125085634.17972-1-yong.wu@mediatek.com>

In mt8195, we have a new IOMMU that is for INFRA IOMMU. its masters
mainly are PCIe and USB. Different with MM IOMMU, all these masters
connect with IOMMU directly, there is no mediatek,larbs property for
infra IOMMU.

Another thing is about PCIe ports. currently the function
"of_iommu_configure_dev_id" only support the id number is 1, But our
PCIe have two ports, one is for reading and the other is for writing.
see more about the PCIe patch in this patchset. Thus, I only list
the reading id here and add the other id in our driver.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/iommu/mediatek,iommu.yaml         | 13 ++++++++++++-
 .../dt-bindings/memory/mt8195-memory-port.h    | 18 ++++++++++++++++++
 include/dt-bindings/memory/mtk-memory-port.h   |  2 ++
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index 9b04630158c8..c528a299afa9 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -79,6 +79,7 @@ properties:
           - mediatek,mt8192-m4u  # generation two
           - mediatek,mt8195-iommu-vdo        # generation two
           - mediatek,mt8195-iommu-vpp        # generation two
+          - mediatek,mt8195-iommu-infra      # generation two
 
       - description: mt7623 generation one
         items:
@@ -129,7 +130,6 @@ required:
   - compatible
   - reg
   - interrupts
-  - mediatek,larbs
   - '#iommu-cells'
 
 allOf:
@@ -161,6 +161,17 @@ allOf:
       required:
         - power-domains
 
+  - if: # The IOMMUs don't have larbs.
+      not:
+        properties:
+          compatible:
+            contains:
+              const: mediatek,mt8195-iommu-infra
+
+    then:
+      required:
+        - mediatek,larbs
+
 additionalProperties: false
 
 examples:
diff --git a/include/dt-bindings/memory/mt8195-memory-port.h b/include/dt-bindings/memory/mt8195-memory-port.h
index eeafad451a1d..fe948fec0688 100644
--- a/include/dt-bindings/memory/mt8195-memory-port.h
+++ b/include/dt-bindings/memory/mt8195-memory-port.h
@@ -387,4 +387,22 @@
 #define M4U_PORT_L28_CAM_DRZS4NO_R1		MTK_M4U_ID(28, 5)
 #define M4U_PORT_L28_CAM_TNCSO_R1		MTK_M4U_ID(28, 6)
 
+/* Infra iommu ports */
+/* PCIe1: read: BIT16; write BIT17. */
+#define IOMMU_PORT_INFRA_PCIE1			MTK_IFAIOMMU_PERI_ID(16)
+/* PCIe0: read: BIT18; write BIT19. */
+#define IOMMU_PORT_INFRA_PCIE0			MTK_IFAIOMMU_PERI_ID(18)
+#define IOMMU_PORT_INFRA_SSUSB_P3_R		MTK_IFAIOMMU_PERI_ID(20)
+#define IOMMU_PORT_INFRA_SSUSB_P3_W		MTK_IFAIOMMU_PERI_ID(21)
+#define IOMMU_PORT_INFRA_SSUSB_P2_R		MTK_IFAIOMMU_PERI_ID(22)
+#define IOMMU_PORT_INFRA_SSUSB_P2_W		MTK_IFAIOMMU_PERI_ID(23)
+#define IOMMU_PORT_INFRA_SSUSB_P1_1_R		MTK_IFAIOMMU_PERI_ID(24)
+#define IOMMU_PORT_INFRA_SSUSB_P1_1_W		MTK_IFAIOMMU_PERI_ID(25)
+#define IOMMU_PORT_INFRA_SSUSB_P1_0_R		MTK_IFAIOMMU_PERI_ID(26)
+#define IOMMU_PORT_INFRA_SSUSB_P1_0_W		MTK_IFAIOMMU_PERI_ID(27)
+#define IOMMU_PORT_INFRA_SSUSB2_R		MTK_IFAIOMMU_PERI_ID(28)
+#define IOMMU_PORT_INFRA_SSUSB2_W		MTK_IFAIOMMU_PERI_ID(29)
+#define IOMMU_PORT_INFRA_SSUSB_R		MTK_IFAIOMMU_PERI_ID(30)
+#define IOMMU_PORT_INFRA_SSUSB_W		MTK_IFAIOMMU_PERI_ID(31)
+
 #endif
diff --git a/include/dt-bindings/memory/mtk-memory-port.h b/include/dt-bindings/memory/mtk-memory-port.h
index 7d64103209af..2f68a0511a25 100644
--- a/include/dt-bindings/memory/mtk-memory-port.h
+++ b/include/dt-bindings/memory/mtk-memory-port.h
@@ -12,4 +12,6 @@
 #define MTK_M4U_TO_LARB(id)		(((id) >> 5) & 0x1f)
 #define MTK_M4U_TO_PORT(id)		((id) & 0x1f)
 
+#define MTK_IFAIOMMU_PERI_ID(port)	MTK_M4U_ID(0, port)
+
 #endif
-- 
2.18.0


WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Will Deacon <will@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Tomasz Figa <tfiga@chromium.org>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<iommu@lists.linux-foundation.org>,
	Hsin-Yi Wang <hsinyi@chromium.org>, <yong.wu@mediatek.com>,
	<youlin.pei@mediatek.com>, <anan.sun@mediatek.com>,
	<xueqi.zhang@mediatek.com>, <yen-chang.chen@mediatek.com>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>,
	<mingyuan.ma@mediatek.com>, <yf.wang@mediatek.com>,
	<libo.kang@mediatek.com>,  <chengci.xu@mediatek.com>
Subject: [PATCH v4 02/35] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU
Date: Tue, 25 Jan 2022 16:56:01 +0800	[thread overview]
Message-ID: <20220125085634.17972-3-yong.wu@mediatek.com> (raw)
In-Reply-To: <20220125085634.17972-1-yong.wu@mediatek.com>

In mt8195, we have a new IOMMU that is for INFRA IOMMU. its masters
mainly are PCIe and USB. Different with MM IOMMU, all these masters
connect with IOMMU directly, there is no mediatek,larbs property for
infra IOMMU.

Another thing is about PCIe ports. currently the function
"of_iommu_configure_dev_id" only support the id number is 1, But our
PCIe have two ports, one is for reading and the other is for writing.
see more about the PCIe patch in this patchset. Thus, I only list
the reading id here and add the other id in our driver.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/iommu/mediatek,iommu.yaml         | 13 ++++++++++++-
 .../dt-bindings/memory/mt8195-memory-port.h    | 18 ++++++++++++++++++
 include/dt-bindings/memory/mtk-memory-port.h   |  2 ++
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index 9b04630158c8..c528a299afa9 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -79,6 +79,7 @@ properties:
           - mediatek,mt8192-m4u  # generation two
           - mediatek,mt8195-iommu-vdo        # generation two
           - mediatek,mt8195-iommu-vpp        # generation two
+          - mediatek,mt8195-iommu-infra      # generation two
 
       - description: mt7623 generation one
         items:
@@ -129,7 +130,6 @@ required:
   - compatible
   - reg
   - interrupts
-  - mediatek,larbs
   - '#iommu-cells'
 
 allOf:
@@ -161,6 +161,17 @@ allOf:
       required:
         - power-domains
 
+  - if: # The IOMMUs don't have larbs.
+      not:
+        properties:
+          compatible:
+            contains:
+              const: mediatek,mt8195-iommu-infra
+
+    then:
+      required:
+        - mediatek,larbs
+
 additionalProperties: false
 
 examples:
diff --git a/include/dt-bindings/memory/mt8195-memory-port.h b/include/dt-bindings/memory/mt8195-memory-port.h
index eeafad451a1d..fe948fec0688 100644
--- a/include/dt-bindings/memory/mt8195-memory-port.h
+++ b/include/dt-bindings/memory/mt8195-memory-port.h
@@ -387,4 +387,22 @@
 #define M4U_PORT_L28_CAM_DRZS4NO_R1		MTK_M4U_ID(28, 5)
 #define M4U_PORT_L28_CAM_TNCSO_R1		MTK_M4U_ID(28, 6)
 
+/* Infra iommu ports */
+/* PCIe1: read: BIT16; write BIT17. */
+#define IOMMU_PORT_INFRA_PCIE1			MTK_IFAIOMMU_PERI_ID(16)
+/* PCIe0: read: BIT18; write BIT19. */
+#define IOMMU_PORT_INFRA_PCIE0			MTK_IFAIOMMU_PERI_ID(18)
+#define IOMMU_PORT_INFRA_SSUSB_P3_R		MTK_IFAIOMMU_PERI_ID(20)
+#define IOMMU_PORT_INFRA_SSUSB_P3_W		MTK_IFAIOMMU_PERI_ID(21)
+#define IOMMU_PORT_INFRA_SSUSB_P2_R		MTK_IFAIOMMU_PERI_ID(22)
+#define IOMMU_PORT_INFRA_SSUSB_P2_W		MTK_IFAIOMMU_PERI_ID(23)
+#define IOMMU_PORT_INFRA_SSUSB_P1_1_R		MTK_IFAIOMMU_PERI_ID(24)
+#define IOMMU_PORT_INFRA_SSUSB_P1_1_W		MTK_IFAIOMMU_PERI_ID(25)
+#define IOMMU_PORT_INFRA_SSUSB_P1_0_R		MTK_IFAIOMMU_PERI_ID(26)
+#define IOMMU_PORT_INFRA_SSUSB_P1_0_W		MTK_IFAIOMMU_PERI_ID(27)
+#define IOMMU_PORT_INFRA_SSUSB2_R		MTK_IFAIOMMU_PERI_ID(28)
+#define IOMMU_PORT_INFRA_SSUSB2_W		MTK_IFAIOMMU_PERI_ID(29)
+#define IOMMU_PORT_INFRA_SSUSB_R		MTK_IFAIOMMU_PERI_ID(30)
+#define IOMMU_PORT_INFRA_SSUSB_W		MTK_IFAIOMMU_PERI_ID(31)
+
 #endif
diff --git a/include/dt-bindings/memory/mtk-memory-port.h b/include/dt-bindings/memory/mtk-memory-port.h
index 7d64103209af..2f68a0511a25 100644
--- a/include/dt-bindings/memory/mtk-memory-port.h
+++ b/include/dt-bindings/memory/mtk-memory-port.h
@@ -12,4 +12,6 @@
 #define MTK_M4U_TO_LARB(id)		(((id) >> 5) & 0x1f)
 #define MTK_M4U_TO_PORT(id)		((id) & 0x1f)
 
+#define MTK_IFAIOMMU_PERI_ID(port)	MTK_M4U_ID(0, port)
+
 #endif
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Will Deacon <will@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Tomasz Figa <tfiga@chromium.org>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<iommu@lists.linux-foundation.org>,
	Hsin-Yi Wang <hsinyi@chromium.org>, <yong.wu@mediatek.com>,
	<youlin.pei@mediatek.com>, <anan.sun@mediatek.com>,
	<xueqi.zhang@mediatek.com>, <yen-chang.chen@mediatek.com>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>,
	<mingyuan.ma@mediatek.com>, <yf.wang@mediatek.com>,
	<libo.kang@mediatek.com>,  <chengci.xu@mediatek.com>
Subject: [PATCH v4 02/35] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU
Date: Tue, 25 Jan 2022 16:56:01 +0800	[thread overview]
Message-ID: <20220125085634.17972-3-yong.wu@mediatek.com> (raw)
In-Reply-To: <20220125085634.17972-1-yong.wu@mediatek.com>

In mt8195, we have a new IOMMU that is for INFRA IOMMU. its masters
mainly are PCIe and USB. Different with MM IOMMU, all these masters
connect with IOMMU directly, there is no mediatek,larbs property for
infra IOMMU.

Another thing is about PCIe ports. currently the function
"of_iommu_configure_dev_id" only support the id number is 1, But our
PCIe have two ports, one is for reading and the other is for writing.
see more about the PCIe patch in this patchset. Thus, I only list
the reading id here and add the other id in our driver.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/iommu/mediatek,iommu.yaml         | 13 ++++++++++++-
 .../dt-bindings/memory/mt8195-memory-port.h    | 18 ++++++++++++++++++
 include/dt-bindings/memory/mtk-memory-port.h   |  2 ++
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index 9b04630158c8..c528a299afa9 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -79,6 +79,7 @@ properties:
           - mediatek,mt8192-m4u  # generation two
           - mediatek,mt8195-iommu-vdo        # generation two
           - mediatek,mt8195-iommu-vpp        # generation two
+          - mediatek,mt8195-iommu-infra      # generation two
 
       - description: mt7623 generation one
         items:
@@ -129,7 +130,6 @@ required:
   - compatible
   - reg
   - interrupts
-  - mediatek,larbs
   - '#iommu-cells'
 
 allOf:
@@ -161,6 +161,17 @@ allOf:
       required:
         - power-domains
 
+  - if: # The IOMMUs don't have larbs.
+      not:
+        properties:
+          compatible:
+            contains:
+              const: mediatek,mt8195-iommu-infra
+
+    then:
+      required:
+        - mediatek,larbs
+
 additionalProperties: false
 
 examples:
diff --git a/include/dt-bindings/memory/mt8195-memory-port.h b/include/dt-bindings/memory/mt8195-memory-port.h
index eeafad451a1d..fe948fec0688 100644
--- a/include/dt-bindings/memory/mt8195-memory-port.h
+++ b/include/dt-bindings/memory/mt8195-memory-port.h
@@ -387,4 +387,22 @@
 #define M4U_PORT_L28_CAM_DRZS4NO_R1		MTK_M4U_ID(28, 5)
 #define M4U_PORT_L28_CAM_TNCSO_R1		MTK_M4U_ID(28, 6)
 
+/* Infra iommu ports */
+/* PCIe1: read: BIT16; write BIT17. */
+#define IOMMU_PORT_INFRA_PCIE1			MTK_IFAIOMMU_PERI_ID(16)
+/* PCIe0: read: BIT18; write BIT19. */
+#define IOMMU_PORT_INFRA_PCIE0			MTK_IFAIOMMU_PERI_ID(18)
+#define IOMMU_PORT_INFRA_SSUSB_P3_R		MTK_IFAIOMMU_PERI_ID(20)
+#define IOMMU_PORT_INFRA_SSUSB_P3_W		MTK_IFAIOMMU_PERI_ID(21)
+#define IOMMU_PORT_INFRA_SSUSB_P2_R		MTK_IFAIOMMU_PERI_ID(22)
+#define IOMMU_PORT_INFRA_SSUSB_P2_W		MTK_IFAIOMMU_PERI_ID(23)
+#define IOMMU_PORT_INFRA_SSUSB_P1_1_R		MTK_IFAIOMMU_PERI_ID(24)
+#define IOMMU_PORT_INFRA_SSUSB_P1_1_W		MTK_IFAIOMMU_PERI_ID(25)
+#define IOMMU_PORT_INFRA_SSUSB_P1_0_R		MTK_IFAIOMMU_PERI_ID(26)
+#define IOMMU_PORT_INFRA_SSUSB_P1_0_W		MTK_IFAIOMMU_PERI_ID(27)
+#define IOMMU_PORT_INFRA_SSUSB2_R		MTK_IFAIOMMU_PERI_ID(28)
+#define IOMMU_PORT_INFRA_SSUSB2_W		MTK_IFAIOMMU_PERI_ID(29)
+#define IOMMU_PORT_INFRA_SSUSB_R		MTK_IFAIOMMU_PERI_ID(30)
+#define IOMMU_PORT_INFRA_SSUSB_W		MTK_IFAIOMMU_PERI_ID(31)
+
 #endif
diff --git a/include/dt-bindings/memory/mtk-memory-port.h b/include/dt-bindings/memory/mtk-memory-port.h
index 7d64103209af..2f68a0511a25 100644
--- a/include/dt-bindings/memory/mtk-memory-port.h
+++ b/include/dt-bindings/memory/mtk-memory-port.h
@@ -12,4 +12,6 @@
 #define MTK_M4U_TO_LARB(id)		(((id) >> 5) & 0x1f)
 #define MTK_M4U_TO_PORT(id)		((id) & 0x1f)
 
+#define MTK_IFAIOMMU_PERI_ID(port)	MTK_M4U_ID(0, port)
+
 #endif
-- 
2.18.0


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  parent reply	other threads:[~2022-01-25  8:57 UTC|newest]

Thread overview: 192+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-25  8:55 [PATCH v4 00/35] MT8195 IOMMU SUPPORT Yong Wu
2022-01-25  8:55 ` Yong Wu
2022-01-25  8:55 ` Yong Wu
2022-01-25  8:55 ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 01/35] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` Yong Wu [this message]
2022-01-25  8:56   ` [PATCH v4 02/35] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 03/35] iommu/mediatek: Fix 2 HW sharing pgtable issue Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-27 10:59   ` AngeloGioacchino Del Regno
2022-01-27 10:59     ` AngeloGioacchino Del Regno
2022-01-27 10:59     ` AngeloGioacchino Del Regno
2022-01-27 10:59     ` AngeloGioacchino Del Regno
2022-01-25  8:56 ` [PATCH v4 04/35] iommu/mediatek: Add list_del in mtk_iommu_remove Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 05/35] iommu/mediatek: Remove clk_disable " Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 06/35] iommu/mediatek: Add mutex for m4u_group and m4u_dom in data Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-27 11:02   ` AngeloGioacchino Del Regno
2022-01-27 11:02     ` AngeloGioacchino Del Regno
2022-01-27 11:02     ` AngeloGioacchino Del Regno
2022-01-27 11:02     ` AngeloGioacchino Del Regno
2022-01-25  8:56 ` [PATCH v4 07/35] iommu/mediatek: Add mutex for data in the mtk_iommu_domain Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-27 11:02   ` AngeloGioacchino Del Regno
2022-01-27 11:02     ` AngeloGioacchino Del Regno
2022-01-27 11:02     ` AngeloGioacchino Del Regno
2022-01-27 11:02     ` AngeloGioacchino Del Regno
2022-01-25  8:56 ` [PATCH v4 08/35] iommu/mediatek: Use kmalloc for protect buffer Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-27 11:08   ` AngeloGioacchino Del Regno
2022-01-27 11:08     ` AngeloGioacchino Del Regno
2022-01-27 11:08     ` AngeloGioacchino Del Regno
2022-01-27 11:08     ` AngeloGioacchino Del Regno
2022-02-16  5:54     ` Yong Wu
2022-02-16  5:54       ` Yong Wu
2022-02-16  5:54       ` Yong Wu
2022-02-16  5:54       ` Yong Wu via iommu
2022-02-16  5:59       ` Tomasz Figa
2022-02-16  5:59         ` Tomasz Figa
2022-02-16  5:59         ` Tomasz Figa
2022-02-16  5:59         ` Tomasz Figa
2022-02-16  8:11         ` Yong Wu
2022-02-16  8:11           ` Yong Wu
2022-02-16  8:11           ` Yong Wu
2022-02-16  8:11           ` Yong Wu via iommu
2022-01-25  8:56 ` [PATCH v4 09/35] iommu/mediatek: Adapt sharing and non-sharing pgtable case Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 10/35] iommu/mediatek: Add 12G~16G support for multi domains Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 11/35] iommu/mediatek: Add a flag DCM_DISABLE Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 12/35] iommu/mediatek: Add a flag NON_STD_AXI Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 13/35] iommu/mediatek: Remove the granule in the tlb flush Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 14/35] iommu/mediatek: Always enable output PA over 32bits in isr Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 15/35] iommu/mediatek: Add SUB_COMMON_3BITS flag Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 16/35] iommu/mediatek: Add IOMMU_TYPE flag Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 17/35] iommu/mediatek: Contain MM IOMMU flow with the MM TYPE Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 18/35] iommu/mediatek: Adjust device link when it is sub-common Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 19/35] iommu/mediatek: Allow IOMMU_DOMAIN_UNMANAGED for PCIe VFIO Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 20/35] iommu/mediatek: Add a PM_CLK_AO flag for infra iommu Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 21/35] iommu/mediatek: Add infra iommu support Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 22/35] iommu/mediatek: Add PCIe support Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 23/35] iommu/mediatek: Add mt8195 support Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 24/35] iommu/mediatek: Only adjust code about register base Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 25/35] iommu/mediatek: Just move code position in hw_init Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 26/35] iommu/mediatek: Separate mtk_iommu_data for v1 and v2 Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 27/35] iommu/mediatek: Remove mtk_iommu.h Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-27 11:15   ` AngeloGioacchino Del Regno
2022-01-27 11:15     ` AngeloGioacchino Del Regno
2022-01-27 11:15     ` AngeloGioacchino Del Regno
2022-01-27 11:15     ` AngeloGioacchino Del Regno
2022-01-25  8:56 ` [PATCH v4 28/35] iommu/mediatek-v1: Just rename mtk_iommu to mtk_iommu_v1 Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 29/35] iommu/mediatek: Add mtk_iommu_bank_data structure Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-27 11:17   ` AngeloGioacchino Del Regno
2022-01-27 11:17     ` AngeloGioacchino Del Regno
2022-01-27 11:17     ` AngeloGioacchino Del Regno
2022-01-27 11:17     ` AngeloGioacchino Del Regno
2022-01-25  8:56 ` [PATCH v4 30/35] iommu/mediatek: Initialise bank HW for each a bank Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 31/35] iommu/mediatek: Change the domid to iova_region_id Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 32/35] iommu/mediatek: Get the proper bankid for multi banks Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-27 11:21   ` AngeloGioacchino Del Regno
2022-01-27 11:21     ` AngeloGioacchino Del Regno
2022-01-27 11:21     ` AngeloGioacchino Del Regno
2022-01-27 11:21     ` AngeloGioacchino Del Regno
2022-01-25  8:56 ` [PATCH v4 33/35] iommu/mediatek: Initialise/Remove for multi bank dev Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56 ` [PATCH v4 34/35] iommu/mediatek: Backup/restore regsiters for multi banks Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-27 11:24   ` AngeloGioacchino Del Regno
2022-01-27 11:24     ` AngeloGioacchino Del Regno
2022-01-27 11:24     ` AngeloGioacchino Del Regno
2022-01-27 11:24     ` AngeloGioacchino Del Regno
2022-01-25  8:56 ` [PATCH v4 35/35] iommu/mediatek: mt8195: Enable multi banks for infra iommu Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-25  8:56   ` Yong Wu
2022-01-27 11:25   ` AngeloGioacchino Del Regno
2022-01-27 11:25     ` AngeloGioacchino Del Regno
2022-01-27 11:25     ` AngeloGioacchino Del Regno
2022-01-27 11:25     ` AngeloGioacchino Del Regno

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