From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Shuah Khan <skhan@linuxfoundation.org>,
Shuah Khan <shuah@kernel.org>
Cc: Alan Hayward <alan.hayward@arm.com>,
Luis Machado <luis.machado@arm.com>,
Salil Akerkar <Salil.Akerkar@arm.com>,
Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
Szabolcs Nagy <szabolcs.nagy@arm.com>,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Luca Salabrino <luca.scalabrino@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kselftest@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v13 07/39] arm64/sme: Early CPU setup for SME
Date: Fri, 8 Apr 2022 12:42:56 +0100 [thread overview]
Message-ID: <20220408114328.1401034-8-broonie@kernel.org> (raw)
In-Reply-To: <20220408114328.1401034-1-broonie@kernel.org>
SME requires similar setup to that for SVE: disable traps to EL2 and
make sure that the maximum vector length is available to EL1, for SME we
have two traps - one for SME itself and one for TPIDR2.
In addition since we currently make no active use of priority control
for SCMUs we map all SME priorities lower ELs may configure to 0, the
architecture specified minimum priority, to ensure that nothing we
manage is able to configure itself to consume excessive resources. This
will need to be revisited should there be a need to manage SME
priorities at runtime.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/include/asm/el2_setup.h | 64 ++++++++++++++++++++++++++++--
1 file changed, 60 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 7f3c87f7a0ce..6430eac98c58 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -143,6 +143,50 @@
.Lskip_sve_\@:
.endm
+/* SME register access and priority mapping */
+.macro __init_el2_nvhe_sme
+ mrs x1, id_aa64pfr1_el1
+ ubfx x1, x1, #ID_AA64PFR1_SME_SHIFT, #4
+ cbz x1, .Lskip_sme_\@
+
+ bic x0, x0, #CPTR_EL2_TSM // Also disable SME traps
+ msr cptr_el2, x0 // Disable copro. traps to EL2
+ isb
+
+ mrs x1, sctlr_el2
+ orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
+ msr sctlr_el2, x1
+ isb
+
+ mov x1, #0 // SMCR controls
+
+ mrs_s x2, SYS_ID_AA64SMFR0_EL1
+ ubfx x2, x2, #ID_AA64SMFR0_FA64_SHIFT, #1 // Full FP in SM?
+ cbz x2, .Lskip_sme_fa64_\@
+
+ orr x1, x1, SMCR_ELx_FA64_MASK
+.Lskip_sme_fa64_\@:
+
+ orr x1, x1, #SMCR_ELx_LEN_MASK // Enable full SME vector
+ msr_s SYS_SMCR_EL2, x1 // length for EL1.
+
+ mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported?
+ ubfx x1, x1, #SYS_SMIDR_EL1_SMPS_SHIFT, #1
+ cbz x1, .Lskip_sme_\@
+
+ msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal
+
+ mrs x1, id_aa64mmfr1_el1 // HCRX_EL2 present?
+ ubfx x1, x1, #ID_AA64MMFR1_HCX_SHIFT, #4
+ cbz x1, .Lskip_sme_\@
+
+ mrs_s x1, SYS_HCRX_EL2
+ orr x1, x1, #HCRX_EL2_SMPME_MASK // Enable priority mapping
+ msr_s SYS_HCRX_EL2, x1
+
+.Lskip_sme_\@:
+.endm
+
/* Disable any fine grained traps */
.macro __init_el2_fgt
mrs x1, id_aa64mmfr0_el1
@@ -153,15 +197,26 @@
mrs x1, id_aa64dfr0_el1
ubfx x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
cmp x1, #3
- b.lt .Lset_fgt_\@
+ b.lt .Lset_debug_fgt_\@
/* Disable PMSNEVFR_EL1 read and write traps */
orr x0, x0, #(1 << 62)
-.Lset_fgt_\@:
+.Lset_debug_fgt_\@:
msr_s SYS_HDFGRTR_EL2, x0
msr_s SYS_HDFGWTR_EL2, x0
- msr_s SYS_HFGRTR_EL2, xzr
- msr_s SYS_HFGWTR_EL2, xzr
+
+ mov x0, xzr
+ mrs x1, id_aa64pfr1_el1
+ ubfx x1, x1, #ID_AA64PFR1_SME_SHIFT, #4
+ cbz x1, .Lset_fgt_\@
+
+ /* Disable nVHE traps of TPIDR2 and SMPRI */
+ orr x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK
+ orr x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK
+
+.Lset_fgt_\@:
+ msr_s SYS_HFGRTR_EL2, x0
+ msr_s SYS_HFGWTR_EL2, x0
msr_s SYS_HFGITR_EL2, xzr
mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
@@ -196,6 +251,7 @@
__init_el2_nvhe_idregs
__init_el2_nvhe_cptr
__init_el2_nvhe_sve
+ __init_el2_nvhe_sme
__init_el2_fgt
__init_el2_nvhe_prepare_eret
.endm
--
2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Shuah Khan <skhan@linuxfoundation.org>,
Shuah Khan <shuah@kernel.org>
Cc: Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
Luis Machado <luis.machado@arm.com>,
Szabolcs Nagy <szabolcs.nagy@arm.com>,
Mark Brown <broonie@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kselftest@vger.kernel.org,
Alan Hayward <alan.hayward@arm.com>,
kvmarm@lists.cs.columbia.edu,
Salil Akerkar <Salil.Akerkar@arm.com>,
Luca Salabrino <luca.scalabrino@arm.com>
Subject: [PATCH v13 07/39] arm64/sme: Early CPU setup for SME
Date: Fri, 8 Apr 2022 12:42:56 +0100 [thread overview]
Message-ID: <20220408114328.1401034-8-broonie@kernel.org> (raw)
In-Reply-To: <20220408114328.1401034-1-broonie@kernel.org>
SME requires similar setup to that for SVE: disable traps to EL2 and
make sure that the maximum vector length is available to EL1, for SME we
have two traps - one for SME itself and one for TPIDR2.
In addition since we currently make no active use of priority control
for SCMUs we map all SME priorities lower ELs may configure to 0, the
architecture specified minimum priority, to ensure that nothing we
manage is able to configure itself to consume excessive resources. This
will need to be revisited should there be a need to manage SME
priorities at runtime.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/include/asm/el2_setup.h | 64 ++++++++++++++++++++++++++++--
1 file changed, 60 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 7f3c87f7a0ce..6430eac98c58 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -143,6 +143,50 @@
.Lskip_sve_\@:
.endm
+/* SME register access and priority mapping */
+.macro __init_el2_nvhe_sme
+ mrs x1, id_aa64pfr1_el1
+ ubfx x1, x1, #ID_AA64PFR1_SME_SHIFT, #4
+ cbz x1, .Lskip_sme_\@
+
+ bic x0, x0, #CPTR_EL2_TSM // Also disable SME traps
+ msr cptr_el2, x0 // Disable copro. traps to EL2
+ isb
+
+ mrs x1, sctlr_el2
+ orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
+ msr sctlr_el2, x1
+ isb
+
+ mov x1, #0 // SMCR controls
+
+ mrs_s x2, SYS_ID_AA64SMFR0_EL1
+ ubfx x2, x2, #ID_AA64SMFR0_FA64_SHIFT, #1 // Full FP in SM?
+ cbz x2, .Lskip_sme_fa64_\@
+
+ orr x1, x1, SMCR_ELx_FA64_MASK
+.Lskip_sme_fa64_\@:
+
+ orr x1, x1, #SMCR_ELx_LEN_MASK // Enable full SME vector
+ msr_s SYS_SMCR_EL2, x1 // length for EL1.
+
+ mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported?
+ ubfx x1, x1, #SYS_SMIDR_EL1_SMPS_SHIFT, #1
+ cbz x1, .Lskip_sme_\@
+
+ msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal
+
+ mrs x1, id_aa64mmfr1_el1 // HCRX_EL2 present?
+ ubfx x1, x1, #ID_AA64MMFR1_HCX_SHIFT, #4
+ cbz x1, .Lskip_sme_\@
+
+ mrs_s x1, SYS_HCRX_EL2
+ orr x1, x1, #HCRX_EL2_SMPME_MASK // Enable priority mapping
+ msr_s SYS_HCRX_EL2, x1
+
+.Lskip_sme_\@:
+.endm
+
/* Disable any fine grained traps */
.macro __init_el2_fgt
mrs x1, id_aa64mmfr0_el1
@@ -153,15 +197,26 @@
mrs x1, id_aa64dfr0_el1
ubfx x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
cmp x1, #3
- b.lt .Lset_fgt_\@
+ b.lt .Lset_debug_fgt_\@
/* Disable PMSNEVFR_EL1 read and write traps */
orr x0, x0, #(1 << 62)
-.Lset_fgt_\@:
+.Lset_debug_fgt_\@:
msr_s SYS_HDFGRTR_EL2, x0
msr_s SYS_HDFGWTR_EL2, x0
- msr_s SYS_HFGRTR_EL2, xzr
- msr_s SYS_HFGWTR_EL2, xzr
+
+ mov x0, xzr
+ mrs x1, id_aa64pfr1_el1
+ ubfx x1, x1, #ID_AA64PFR1_SME_SHIFT, #4
+ cbz x1, .Lset_fgt_\@
+
+ /* Disable nVHE traps of TPIDR2 and SMPRI */
+ orr x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK
+ orr x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK
+
+.Lset_fgt_\@:
+ msr_s SYS_HFGRTR_EL2, x0
+ msr_s SYS_HFGWTR_EL2, x0
msr_s SYS_HFGITR_EL2, xzr
mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
@@ -196,6 +251,7 @@
__init_el2_nvhe_idregs
__init_el2_nvhe_cptr
__init_el2_nvhe_sve
+ __init_el2_nvhe_sme
__init_el2_fgt
__init_el2_nvhe_prepare_eret
.endm
--
2.30.2
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Shuah Khan <skhan@linuxfoundation.org>,
Shuah Khan <shuah@kernel.org>
Cc: Alan Hayward <alan.hayward@arm.com>,
Luis Machado <luis.machado@arm.com>,
Salil Akerkar <Salil.Akerkar@arm.com>,
Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
Szabolcs Nagy <szabolcs.nagy@arm.com>,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Luca Salabrino <luca.scalabrino@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kselftest@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v13 07/39] arm64/sme: Early CPU setup for SME
Date: Fri, 8 Apr 2022 12:42:56 +0100 [thread overview]
Message-ID: <20220408114328.1401034-8-broonie@kernel.org> (raw)
In-Reply-To: <20220408114328.1401034-1-broonie@kernel.org>
SME requires similar setup to that for SVE: disable traps to EL2 and
make sure that the maximum vector length is available to EL1, for SME we
have two traps - one for SME itself and one for TPIDR2.
In addition since we currently make no active use of priority control
for SCMUs we map all SME priorities lower ELs may configure to 0, the
architecture specified minimum priority, to ensure that nothing we
manage is able to configure itself to consume excessive resources. This
will need to be revisited should there be a need to manage SME
priorities at runtime.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/include/asm/el2_setup.h | 64 ++++++++++++++++++++++++++++--
1 file changed, 60 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 7f3c87f7a0ce..6430eac98c58 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -143,6 +143,50 @@
.Lskip_sve_\@:
.endm
+/* SME register access and priority mapping */
+.macro __init_el2_nvhe_sme
+ mrs x1, id_aa64pfr1_el1
+ ubfx x1, x1, #ID_AA64PFR1_SME_SHIFT, #4
+ cbz x1, .Lskip_sme_\@
+
+ bic x0, x0, #CPTR_EL2_TSM // Also disable SME traps
+ msr cptr_el2, x0 // Disable copro. traps to EL2
+ isb
+
+ mrs x1, sctlr_el2
+ orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
+ msr sctlr_el2, x1
+ isb
+
+ mov x1, #0 // SMCR controls
+
+ mrs_s x2, SYS_ID_AA64SMFR0_EL1
+ ubfx x2, x2, #ID_AA64SMFR0_FA64_SHIFT, #1 // Full FP in SM?
+ cbz x2, .Lskip_sme_fa64_\@
+
+ orr x1, x1, SMCR_ELx_FA64_MASK
+.Lskip_sme_fa64_\@:
+
+ orr x1, x1, #SMCR_ELx_LEN_MASK // Enable full SME vector
+ msr_s SYS_SMCR_EL2, x1 // length for EL1.
+
+ mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported?
+ ubfx x1, x1, #SYS_SMIDR_EL1_SMPS_SHIFT, #1
+ cbz x1, .Lskip_sme_\@
+
+ msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal
+
+ mrs x1, id_aa64mmfr1_el1 // HCRX_EL2 present?
+ ubfx x1, x1, #ID_AA64MMFR1_HCX_SHIFT, #4
+ cbz x1, .Lskip_sme_\@
+
+ mrs_s x1, SYS_HCRX_EL2
+ orr x1, x1, #HCRX_EL2_SMPME_MASK // Enable priority mapping
+ msr_s SYS_HCRX_EL2, x1
+
+.Lskip_sme_\@:
+.endm
+
/* Disable any fine grained traps */
.macro __init_el2_fgt
mrs x1, id_aa64mmfr0_el1
@@ -153,15 +197,26 @@
mrs x1, id_aa64dfr0_el1
ubfx x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
cmp x1, #3
- b.lt .Lset_fgt_\@
+ b.lt .Lset_debug_fgt_\@
/* Disable PMSNEVFR_EL1 read and write traps */
orr x0, x0, #(1 << 62)
-.Lset_fgt_\@:
+.Lset_debug_fgt_\@:
msr_s SYS_HDFGRTR_EL2, x0
msr_s SYS_HDFGWTR_EL2, x0
- msr_s SYS_HFGRTR_EL2, xzr
- msr_s SYS_HFGWTR_EL2, xzr
+
+ mov x0, xzr
+ mrs x1, id_aa64pfr1_el1
+ ubfx x1, x1, #ID_AA64PFR1_SME_SHIFT, #4
+ cbz x1, .Lset_fgt_\@
+
+ /* Disable nVHE traps of TPIDR2 and SMPRI */
+ orr x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK
+ orr x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK
+
+.Lset_fgt_\@:
+ msr_s SYS_HFGRTR_EL2, x0
+ msr_s SYS_HFGWTR_EL2, x0
msr_s SYS_HFGITR_EL2, xzr
mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
@@ -196,6 +251,7 @@
__init_el2_nvhe_idregs
__init_el2_nvhe_cptr
__init_el2_nvhe_sve
+ __init_el2_nvhe_sme
__init_el2_fgt
__init_el2_nvhe_prepare_eret
.endm
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-04-08 11:55 UTC|newest]
Thread overview: 123+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-08 11:42 [PATCH v13 00/39] arm64/sme: Initial support for the Scalable Matrix Extension Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` [PATCH v13 01/39] kselftest/arm64: Fix comment for ptrace_sve_get_fpsimd_data() Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` [PATCH v13 02/39] kselftest/arm64: Remove assumption that tasks start FPSIMD only Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` [PATCH v13 03/39] kselftest/arm64: Validate setting via FPSIMD and read via SVE regsets Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` [PATCH v13 04/39] arm64/sme: Provide ABI documentation for SME Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-13 14:31 ` Szabolcs Nagy
2022-04-13 14:31 ` Szabolcs Nagy
2022-04-13 14:31 ` Szabolcs Nagy
2022-04-08 11:42 ` [PATCH v13 05/39] arm64/sme: System register and exception syndrome definitions Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` [PATCH v13 06/39] arm64/sme: Manually encode SME instructions Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` Mark Brown [this message]
2022-04-08 11:42 ` [PATCH v13 07/39] arm64/sme: Early CPU setup for SME Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` [PATCH v13 08/39] arm64/sme: Basic enumeration support Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` [PATCH v13 09/39] arm64/sme: Identify supported SME vector lengths at boot Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` [PATCH v13 10/39] arm64/sme: Implement sysctl to set the default vector length Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:42 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 11/39] arm64/sme: Implement vector length configuration prctl()s Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 12/39] arm64/sme: Implement support for TPIDR2 Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 13/39] arm64/sme: Implement SVCR context switching Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 14/39] arm64/sme: Implement streaming SVE " Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 15/39] arm64/sme: Implement ZA " Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 16/39] arm64/sme: Implement traps and syscall handling for SME Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 17/39] arm64/sme: Disable ZA and streaming mode when handling signals Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 18/39] arm64/sme: Implement streaming SVE signal handling Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 19/39] arm64/sme: Implement ZA " Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 20/39] arm64/sme: Implement ptrace support for streaming mode SVE registers Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 21/39] arm64/sme: Add ptrace support for ZA Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 22/39] arm64/sme: Disable streaming mode and ZA when flushing CPU state Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 23/39] arm64/sme: Save and restore streaming mode over EFI runtime calls Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 24/39] KVM: arm64: Hide SME system registers from guests Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 25/39] KVM: arm64: Trap SME usage in guest Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 26/39] KVM: arm64: Handle SME host state when running guests Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 27/39] arm64/sme: Provide Kconfig for SME Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 28/39] kselftest/arm64: Add manual encodings for SME instructions Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 29/39] kselftest/arm64: sme: Add SME support to vlset Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 30/39] kselftest/arm64: Add tests for TPIDR2 Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 31/39] kselftest/arm64: Extend vector configuration API tests to cover SME Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 32/39] kselftest/arm64: sme: Provide streaming mode SVE stress test Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 33/39] kselftest/arm64: signal: Handle ZA signal context in core code Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 34/39] kselftest/arm64: Add stress test for SME ZA context switching Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 35/39] kselftest/arm64: signal: Add SME signal handling tests Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 36/39] kselftest/arm64: Add streaming SVE to SVE ptrace tests Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 37/39] kselftest/arm64: Add coverage for the ZA ptrace interface Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 38/39] kselftest/arm64: Add SME support to syscall ABI test Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` [PATCH v13 39/39] selftests/arm64: Add a testcase for handling of ZA on clone() Mark Brown
2022-04-08 11:43 ` Mark Brown
2022-04-08 11:43 ` Mark Brown
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