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From: Stephen Boyd <sboyd@kernel.org>
To: Conor Dooley <conor.dooley@microchip.com>,
	linux-clk@vger.kernel.org, mturquette@baylibre.com
Cc: daire.mcnamara@microchip.com, linux-riscv@lists.infradead.org,
	palmer@rivosinc.com, andrew@lunn.ch, linux@armlinux.org.uk,
	Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v2] clk: microchip: mpfs: don't reset disabled peripherals
Date: Thu, 21 Apr 2022 19:35:10 -0700	[thread overview]
Message-ID: <20220422023512.C01EEC385A7@smtp.kernel.org> (raw)
In-Reply-To: <20220411072340.740981-1-conor.dooley@microchip.com>

Quoting Conor Dooley (2022-04-11 00:23:41)
> The current clock driver for PolarFire SoC puts the hardware behind
> "periph" clocks into reset if their clock is disabled. CONFIG_PM was
> recently added to the riscv defconfig and exposed issues caused by this
> behaviour, where the Cadence GEM was being put into reset between its
> bringup & the PHY bringup:
> 
> https://lore.kernel.org/linux-riscv/9f4b057d-1985-5fd3-65c0-f944161c7792@microchip.com/
> 
> Fix this (for now) by removing the reset from mpfs_periph_clk_disable.
> 
> Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC")
> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---

Applied to clk-fixes

WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Conor Dooley <conor.dooley@microchip.com>,
	linux-clk@vger.kernel.org, mturquette@baylibre.com
Cc: daire.mcnamara@microchip.com, linux-riscv@lists.infradead.org,
	palmer@rivosinc.com, andrew@lunn.ch, linux@armlinux.org.uk,
	Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v2] clk: microchip: mpfs: don't reset disabled peripherals
Date: Thu, 21 Apr 2022 19:35:10 -0700	[thread overview]
Message-ID: <20220422023512.C01EEC385A7@smtp.kernel.org> (raw)
In-Reply-To: <20220411072340.740981-1-conor.dooley@microchip.com>

Quoting Conor Dooley (2022-04-11 00:23:41)
> The current clock driver for PolarFire SoC puts the hardware behind
> "periph" clocks into reset if their clock is disabled. CONFIG_PM was
> recently added to the riscv defconfig and exposed issues caused by this
> behaviour, where the Cadence GEM was being put into reset between its
> bringup & the PHY bringup:
> 
> https://lore.kernel.org/linux-riscv/9f4b057d-1985-5fd3-65c0-f944161c7792@microchip.com/
> 
> Fix this (for now) by removing the reset from mpfs_periph_clk_disable.
> 
> Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC")
> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---

Applied to clk-fixes

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  reply	other threads:[~2022-04-22  2:35 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-11  7:23 [PATCH v2] clk: microchip: mpfs: don't reset disabled peripherals Conor Dooley
2022-04-11  7:23 ` Conor Dooley
2022-04-22  2:35 ` Stephen Boyd [this message]
2022-04-22  2:35   ` Stephen Boyd
2022-04-22  6:26   ` Conor.Dooley
2022-04-22  6:26     ` Conor.Dooley

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