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From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com,
	peter.maydell@linaro.org, richard.henderson@linaro.org,
	"Víctor Colombo" <victor.colombo@eldorado.org.br>
Subject: [PULL 12/30] target/ppc: Remove msr_le macro
Date: Thu,  5 May 2022 15:49:20 -0300	[thread overview]
Message-ID: <20220505184938.351866-13-danielhb413@gmail.com> (raw)
In-Reply-To: <20220505184938.351866-1-danielhb413@gmail.com>

From: Víctor Colombo <victor.colombo@eldorado.org.br>

msr_le macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-5-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
 target/ppc/cpu.h        |  2 +-
 target/ppc/cpu_init.c   |  2 +-
 target/ppc/gdbstub.c    |  2 +-
 target/ppc/mem_helper.c | 16 ++++++++--------
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 8f1dc4cb15..c561d664de 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -355,6 +355,7 @@ typedef enum {
 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 
 FIELD(MSR, PR, MSR_PR, 1)
+FIELD(MSR, LE, MSR_LE, 1)
 
 /* PMU bits */
 #define MMCR0_FC     PPC_BIT(32)         /* Freeze Counters  */
@@ -486,7 +487,6 @@ FIELD(MSR, PR, MSR_PR, 1)
 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
 #define msr_ds   ((env->msr >> MSR_DS)   & 1)
-#define msr_le   ((env->msr >> MSR_LE)   & 1)
 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 
 #define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ac16a64846..0c6b83406e 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7210,7 +7210,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
 
     cpu_synchronize_state(cs);
 
-    return !msr_le;
+    return !FIELD_EX64(env->msr, MSR, LE);
 }
 
 #ifdef CONFIG_TCG
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 1252429a2a..1a0b9ca82c 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -95,7 +95,7 @@ static int ppc_gdb_register_len(int n)
 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
 {
 #ifndef CONFIG_USER_ONLY
-    if (!msr_le) {
+    if (!FIELD_EX64(env->msr, MSR, LE)) {
         /* do nothing */
     } else if (len == 4) {
         bswap32s((uint32_t *)mem_buf);
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index fba7f84b7a..9af135e88e 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -33,9 +33,9 @@
 static inline bool needs_byteswap(const CPUPPCState *env)
 {
 #if TARGET_BIG_ENDIAN
-  return msr_le;
+  return FIELD_EX64(env->msr, MSR, LE);
 #else
-  return !msr_le;
+  return !FIELD_EX64(env->msr, MSR, LE);
 #endif
 }
 
@@ -470,8 +470,8 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
 #endif
 
 /*
- * We use msr_le to determine index ordering in a vector.  However,
- * byteswapping is not simply controlled by msr_le.  We also need to
+ * We use MSR_LE to determine index ordering in a vector.  However,
+ * byteswapping is not simply controlled by MSR_LE.  We also need to
  * take into account endianness of the target.  This is done for the
  * little-endian PPC64 user-mode target.
  */
@@ -484,7 +484,7 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
         int adjust = HI_IDX * (n_elems - 1);                    \
         int sh = sizeof(r->element[0]) >> 1;                    \
         int index = (addr & 0xf) >> sh;                         \
-        if (msr_le) {                                           \
+        if (FIELD_EX64(env->msr, MSR, LE)) {                    \
             index = n_elems - index - 1;                        \
         }                                                       \
                                                                 \
@@ -511,7 +511,7 @@ LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
         int adjust = HI_IDX * (n_elems - 1);                            \
         int sh = sizeof(r->element[0]) >> 1;                            \
         int index = (addr & 0xf) >> sh;                                 \
-        if (msr_le) {                                                   \
+        if (FIELD_EX64(env->msr, MSR, LE)) {                            \
             index = n_elems - index - 1;                                \
         }                                                               \
                                                                         \
@@ -545,7 +545,7 @@ void helper_##name(CPUPPCState *env, target_ulong addr,                 \
     t.s128 = int128_zero();                                             \
     if (nb) {                                                           \
         nb = (nb >= 16) ? 16 : nb;                                      \
-        if (msr_le && !lj) {                                            \
+        if (FIELD_EX64(env->msr, MSR, LE) && !lj) {                     \
             for (i = 16; i > 16 - nb; i--) {                            \
                 t.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC());   \
                 addr = addr_add(env, addr, 1);                          \
@@ -576,7 +576,7 @@ void helper_##name(CPUPPCState *env, target_ulong addr,           \
     }                                                             \
                                                                   \
     nb = (nb >= 16) ? 16 : nb;                                    \
-    if (msr_le && !lj) {                                          \
+    if (FIELD_EX64(env->msr, MSR, LE) && !lj) {                   \
         for (i = 16; i > 16 - nb; i--) {                          \
             cpu_stb_data_ra(env, addr, xt->VsrB(i - 1), GETPC()); \
             addr = addr_add(env, addr, 1);                        \
-- 
2.32.0



  parent reply	other threads:[~2022-05-05 19:43 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-05 18:49 [PULL 00/30] ppc queue Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 01/30] target/ppc: initialize 'val' union in kvm_get_one_spr() Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 02/30] target/ppc: init 'lpcr' in kvmppc_enable_cap_large_decr() Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 03/30] target/ppc: init 'sregs' in kvmppc_put_books_sregs() Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 04/30] target/ppc: init 'rmmu_info' in kvm_get_radix_page_info() Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 05/30] target/ppc: Fix BookE debug interrupt generation Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 06/30] vhost-user: Use correct macro name TARGET_PPC64 Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 07/30] ppc/xive: Always recompute the PIPR when pushing an OS context Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 08/30] ppc/xive: Update the state of the External interrupt signal Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 09/30] target/ppc: Remove fpscr_* macros from cpu.h Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 10/30] target/ppc: Remove unused msr_* macros Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 11/30] target/ppc: Remove msr_pr macro Daniel Henrique Barboza
2022-05-05 18:49 ` Daniel Henrique Barboza [this message]
2022-05-05 18:49 ` [PULL 13/30] target/ppc: Remove msr_ds macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 14/30] target/ppc: Remove msr_ile macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 15/30] target/ppc: Remove msr_ee macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 16/30] target/ppc: Remove msr_ce macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 17/30] target/ppc: Remove msr_pow macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 18/30] target/ppc: Remove msr_me macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 19/30] target/ppc: Remove msr_gs macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 20/30] target/ppc: Remove msr_fp macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 21/30] target/ppc: Remove msr_cm macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 22/30] target/ppc: Remove msr_ir macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 23/30] target/ppc: Remove msr_dr macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 24/30] target/ppc: Remove msr_ep macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 25/30] target/ppc: Remove msr_fe0 and msr_fe1 macros Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 26/30] target/ppc: Remove msr_ts macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 27/30] target/ppc: Remove msr_hv macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 28/30] target/ppc: Remove msr_de macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 29/30] target/ppc: Add unused msr bits FIELDs Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 30/30] target/ppc: Change MSR_* to follow POWER ISA numbering convention Daniel Henrique Barboza
2022-05-06  4:17 ` [PULL 00/30] ppc queue Richard Henderson

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